Tessent: Scan and ATPG

Module 3

Scan Insertion and

Configuration
 Objectives

Upon completion of this module, you will be able to:

 Use DFTAdvisor to insert full scan.

 Write a scan-inserted netlist file.
 Write ATPG setup files.
 Insert test logic.
 Create, configure, and balance scan chains.
 Edit a scan chain order file and change the order of the scan
cells.

3-2 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 DFTAdvisor Tool Flow: An Overview

DFTAdvisor

Tessent FastScan/
Tessent TestKompress

3-3 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Invoking DFTAdvisor
 The DFTAdvisor executable is installed at:
<install_dir>/bin/dftadvisor
 Invocation requirements:
 A non-scan inserted design netlist in Verilog
 DFT library

3-4 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Invoking DFTAdvisor (Cont.)

Invocation:
shell> dftadvisor design.v -verilog \
-lib dft.lib -log transcript.log –replace

Use the -log <filename> option

to write detailed session information to a file

Helpful tip

3-5 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 DFTAdvisor Tool Flow With Commands
design.v
dft.lib

Non-scan
Netlist DFT Library
Commands:
SETUP> ADD INput Constraints
Setup SETUP> ADD CLocks

Scan/Test Logic
Configuration // typically use defaults

Design Rule
Checking SETUP> SET SYstem Mode Dft

Scan
DFT> RUN
Identification

Scan/Test Logic
DFT> INSert TEst Logic -NUmber 8
Insertion

Write Results DFT> WRIte NEtlist scan_design.v -Verilog

DFT> WRIte ATpg Setup scan_design
DFT> EXIt

Scan Inserted ATPG Setup Test

Setup information
Netlist Dofile Procedure File for ATPG
scan_design.v scan_design.dofile scan_design.procfile

3-6 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Methodology: Scan Cells

DFTAdvisor

 Specify Mux scan as scan cell type.

SETUP> SET SCan Type Mux scan // default

3-7 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 SETUP
DFTAdvisor
 FIRST: Define input constraints.
 Define during setup mode.
 Pin constraints are signals that are held at a
constant value during test.
SETUP> ADD INput Constraints control -C1
//constrain to constant 1
set

S
D Q
0

clk
1
R
control

r_n

3-8 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 SETUP (Cont.)
 SECOND: Define clocks.
set
 Clocks are primary input signals
that asynchronously change the
state of sequential logic elements.
– clocks
S
D Q – sets
– resets
clk – RAM read/write clocks
R
control
SETUP> ADD Clocks 0 clk set
SETUP> ADD Clocks 1 r_n

r_n
Off state Primary input pin

3-9 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 SETUP (Cont.)
 The ANAlyze COntrol Signals command identifies and
optionally defines primary inputs of control signals.
 Clocks, set, reset, write-control, read-control, etc.
 Performs the flattening process automatically.
 Does not support gated clocks.
 Default is -report only.
 -verbose enables the tool to issue messages indicating why certain
control signals are not reported as controllable.
 -Auto_fix specifies the tool to define all identified primary inputs.
– Limited capability.
– Does not always correctly identify off states.
– Hard to determine off states of every clock in the clock cone.
• Important because you do not want scan cells to capture data during the clock’s
off state.
• Use ADD Clocks command instead.

3-10 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan/Test Logic Configuration

DFTAdvisor

Perform Scan/Test Logic Configuration

 Default settings exist
 User can specify
- Scan methodology
- Test pin names
- Areas not to scan
- Test logic options
- Existing scan
- Circuit clocks

3-11 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Set Test Logic Configuration
 User-defined setting options in SETUP mode:
 Scan Methodology
SET SCan Type {Mux scan | Lssd | Clocked_scan}
(Setup mode)

 Test Pin namings:

SETup SCan Insertion [–Ten pathname][-TClk pathname]
[-SClk pathname][-SMclk pathname][-SSclk pathname]
[-SET pathname][-RESet pathname]
[-Write pathname][-REAd pathname][-Muxed | -Disabled |-Gated]
[-Active {High | Low}]
(Setup mode)

|
SETup SCan Pins {Input | Output} [-INDexed |-Bused][-Prefix
base_name][-INItial index#][-Modifier incr_index#]
[-Suffix suffix_name]
(All modes)

ADD SCan Pins chain_name scan_input_pin scan_output_pin [-Clock

pin_name][-CUt][-Registered]
[-Top primary_input_pin primary_out_pin]
(All modes)

3-12 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Set Test Logic Configuration (Cont.)
 Control bidirectional pins
SET BIdi Gating [OFF| ON |Scan][-Control {Sen | Ten}]
[-Direction {Input | Output}][-Top {ALl |
primary_bidi_pin…}] [-Force_gating]
(Setup mode)
 Control tri-state devices
SET Tristate Gating {OFF | ON | Busdrivers | Scan |
primary_input_or_output… | Decoded} [-Control {Sen | Ten}
[-Force_gating]
(Setup mode)
 Test logic options
SET TEst Logic{-Set {ON | OFf} | -Reset {ON | OFf}|
-Clock {ON | OFf} | -Ram {ON | Off}}…
(Setup mode)
 Areas not to scan
ADD NONscan Instances pathname…|instance_expression
{-INStance | -Control_signal | -Module}
(All modes except DFT mode only for –Control option)

3-13 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Adding Test Logic
 Some designs contain uncontrollable clock circuitry.

 Test logic is added to make the circuit scannable.

3-14 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Adding Test Logic (Cont.)

Non-Scannable Scannable

 Required modifications:
 Specify which types of control lines are controllable.
SETUP> SET Test Logic -Set ON -Clock on
 Disable set/reset.
SETUP> ADD CEll Models -Type OR <cell name>
 Activate test mode with “test enable” signal.
SETUP> ADD CEll Models -Type MUX selector data0 data <cell name>
– Or: gates for test logic can be defined by “cell-type” in the library model.

3-15 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Set Test Logic Configuration (Defining Non-Scan Areas)
 Excluding the TAP controller from scan

Before Run After Run

CORE 2
Scan-inserted

CORE 1

TAP_C TAP_C
Scan-inserted

TOP TOP

Non-scanned
SETUP> ADD NOnscan Instance /TOP/TAP_C -IN

3-16 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Design Rule Checking (DRC)

DFTAdvisor

3-17 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Specific DRCs
 General rules (G rules)
 Checks for gross scan definition errors
 Trace rules (T rules)
 Uses test procedure files to trace scan chains
– Bus contention or data shifted through scan chains
 Scannability rules (S rules)
 Ensures that DFTAdvisor can safely
convert a sequential element into a scan element
 Checks scannability during DRC
– S1 rule checking: DFT> REPort DRc Rules
• Ensures that all clocks off- sequential
elements are stable and inactive
– S2 rule checking
• Ensure that defined clocks capture data
when all other clocks are off
Displays all failing DRC violations

3-18 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Identification

DFTAdvisor

Commands:
DFT> RUN
DFT> REPort STatistics

3-19 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan/Test Logic Insertion

DFTAdvisor

Command:
DFT> INSert TEst Logic -NUmber 4

3-20 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan/Test Logic Insertion (Cont.)
 To display results:
DFT> REPort SCan Chains
DFT> REPort TEst Logic

DFT> INSert TEst Logic -NUmber 2

// WARNING: Flattened model has been freed
DFT> REPort SCan Chains
chain = chain1 group = dummy input = /scan_in1 output = /scan_out1 length = 4
scan_enable = /scan_en clock = /clk
reset = /rst
chain = chain2 group = dummy input = /scan_in2 output = /scan_out2 length = 3
scan_enable = /scan_en clock = /clk
reset = /rst
DFT> REPort TEst Logic
New pins added in top module: example_ckt
/scan_in1
/scan_out1
/scan_in2
/scan_out2
/scan_en
Number of new pins inserted = 5

3-21 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Write Results
DFTAdvisor

Commands:
DFT> WRIte NEtlist scan_design.v
DFT> WRIte ATpg Setup scan_design

3-22 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Methodology: Full Scan
design.v dft.lib

Non-scan DFT Library

Netlist DFTAdvisor

Setup

Scan/Test Logic
 Specify Full scan for scan identification.
Configuration
> SETup SCan Identification Full scan //default
Design Rule
Checking
Scan
Identification
Scan/Test Logic
Insertion

Write Results

Scan Inserted ATPG Dofile Test

Netlist Procedure File

3-23 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Methodology: Full Scan versus Partial Scan
 Full scan (default)
 Most commonly used
 Converts all memory elements to scan
– Sometimes a few non-scan restrictions
 Provides high test coverage/high quality
 Uses a combinational ATPG tool
– Requires minimal test generation effort
 Partial scan
 Not commonly used
 Converts a portion of memory elements to scan
 Requires less silicon area
– Increases CPU time to obtain a certain test coverage

3-24 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Methodology: DFT Library and Scan Identification
design.v dft.lib
 The DFT library:
Non-scan
Netlist
DFTAdvisor DFT Library  A model description defines a
single cell in the technology library.
Setup

Scan/Test Logic
 A cell description (model or macro)
Configuration
describes a component in a
Design Rule
Checking specified design.
Scan
Identification
 A library is simply a set of models.
Scan/Test Logic
Insertion

Write Results Non scan cell model

// ==================================
// Model: DFF
// ==================================
Scan Inserted Test
Netlist ATPG Dofile Procedure File
model DFF (PRE, CLR, CLK, D, Q, QB) (
input (PRE, CLR, D) ( )
input (CLK) (clock = rise_edge;)
output(Q, QB) (primitive = _dff (PRE, CLR, CLK, D
Q, QB) ;
)

3-25 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Methodology: DFT library and Scan Identification
(Cont.)
 If a library model is a scan cell, the model description
contains a scan definition attribute:
 Provides information for mapping non-scan sequential models
(dffs and latches) to their associated scan cell models.
//========================================== Original
Model: DFF PRE Flip-Flop
//===========================================
D Q
model DFF ( PRE,CLR,CLK,D, Q, QB) (
input ( PRE, CLR, D) () CLK QB
input(CLK) (clock = rise_edge;)
output(Q QB) (primitive = _dff(PRE,CLR,CLK,D,QB);
) CLR
//============================================= Replaced with:
Model: MUX_SCAN _CELL Mux_Scan_Cell
//==============================================
model MUX_SCAN_CELL (PRE, CLR, SC_IN, SC_EN, CLK, D, Q, QB) (
scan_definition (
type = mux_scan PRE
scan_in = SC_IN;
scan_enable = SC_EN; D N_2 DFF 1
scan_out = Q, QB;
non_scan_model = DFF ( PRE, CLR, CLK, D, Q, QB); SC_IN D Q
) MUX 1
input (PRE, CLR, SC_IN, SC_EN, CLK ()
SC_EN DFF
intern(N_2) (primitive = _mux mux1 (D, SC_IN, SC_EN,N_2);) CLK QB
output(Q, QB) (primitive = _dff dff1(PRE, CLR, CLK, N_2, Q, QB);)
)
//============================================ CLR

3-26 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Test Logic
 Why do we add test logic?
 Some designs contain uncontrollable clock circuitry.
 Sequential devices must be controllable to be converted to scan.
 RAM and three-state logic must be controllable to be testable.

Before After
Uncontrollable Clock Added Test Logic
CL= combinational
Test_en
logic

DRQ CL D RQ DRQ CL D RQ
Sc_in Sc_in Sc_in Sc_in
Sc_en Sc_en Sc_en Sc_en
CK CK CK CK

3-27 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Test Logic (Cont.)
 To add test logic circuitry, DFTAdvisor uses a number of
combinational gates from the ATPG library. For example:
 AND MUX Latch
 OR INV
 Can also use the ADD Cell Models command.
 A cell_type attribute defines valid test logic.
// =========================
// Model: AN2
// =========================

model AN2 (A, B, Z) (

cell_type = AND;
input (A, B) ( )
output (Z) (function = A * B;)
)

3-28 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Test Logic (Cont.)
design.v dft.lib

DFTAdvisor
 Define library models used for test
Non-scan DFT Library
Netlist logic:
Setup

Scan/Test Logic
SETUP> ADD CEll Models
Configuration
dftlib_model
Design Rule
Checking
 Or automatically defined by DFT library
Scan
Identification
Scan/Test Logic
if the model has a cell_type attribute.
Insertion

Write Results

 Generate scannability check results

for non-scan instances:
Scan Inserted
Netlist
ATPG Dofile Test
Procedure File DFT> REPort DFT Check

Helpful Tip: SETUP> ANAlyze COntrol Signals

Lists identified pins that SETUP> ADD Clocks Clk 0
require test logic.
SETUP> SET TEst Logic -set on
SETUP> SET SYstem Mode dft
DFT> REPort DFT Check

3-29 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Test Logic: Defining Library Models

 Define library models when

inserting test logic for the
// command: INSert TEst Logic
// Warning: Flattened model has been freed
following situations:
// command: write atpg setup pipe_setup -procfile -rep  Set/reset clock access.
// command: write netlist pipe_netlist.v -verilog -replace
// Writing VERILOG netlist ...  Lockup latch between clock
// command: REPort TEst Logic
New pins added in top module: pipe
domains.
/scan_in1  RAM control.
/scan_en
Number of new pins inserted = 2  Three-state bus control.
Typically added
 Control points. in 2nd pass
 Observe points.
Inserted test logic  Display added test logic during
scan insertion:
DFT> REPort TEst Logic

3-30 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Pins

 Fault sites include only:

 PI, PO.
 Library model pins.
 DFT primitive pins (internal).
 Pins are identified by unique pin names:
– /I116/q
 Three types of pins:
 Inputs (top-level, primary input).
 Output (top-level, primary output).
 Bidi.

3-31 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Fault Locations
 By default, faults reside at the inputs and outputs of library
models.
 Faults can reside at the inputs and outputs of gates within
library models instead if you turn internal faulting on.

3-32 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Defining Pins
design.v dft.lib
DFTAdvisor
Non-scan DFT Library
Netlist

Setup

Scan/Test Logic  Assign scan input and scan output pin

Configuration
connections to existing logic:
Design Rule
Checking
SETUP> ADD SCan Pins Chain1 /U1/O \
Scan
Identification /U2/I
Scan/Test Logic
Insertion
 Assign scan control pin connections:
Write Results
SETUP> SETup SCan Insertion \
-TEN test_en
SETUP> SET Scan Enable my_scan_en

Scan Inserted ATPG Dofile Test

Netlist Procedure File

3-33 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Defining Pins (Cont.)
Connect to scan in Connect to scan out
top

I
Pad I Pad O
O Before scan
Si_1 So_1
U1 U2

A
B Y

D Q D Q D Q SO

CLK
X
test_enable

SETUP> ADD SCan Pins /U1/O /U2/I

SETUP> SETup SCan Insertion -TEN test_enable
SETUP> SET Scan Enable my_scan_enable

3-34 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Defining Pins (Cont.)

top

I
Pad O Pad
I O
Si_1 After scan So_1
U1 U2

A
B Y

my_scan_en Pad

D Q SO
D Q D Q

CLK
X

test_enable

DFT> INSert TEst Logic

Added test logic
Denotes new top level pins

3-35 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Clocks

 The following applies to clocks:

 Most designs have multiple clocks.
 Clocks have a defined “off-state”
 Clocks have two types of behavior:
– Shift clocks shift data through the scan chain.
– Capture clocks capture data into scan cells.

Off-state refers to
primary input.
CLK
Logic
cloud

CLK

3-36 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clock Issues
 Designs with multiple clock domains can produce clock
skew during test.
 Different clock inputs and clock edges can cause the
following skew problems:
 Shifting data through scan chains.
 Capturing data into scan chains.

Clk1

Clk2 Design
Clk3 Block
Clk4 A

Design
Block
B

3-37 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clock Issues (Cont.)
 During shift, all shift clocks are pulsed at the same frequency
and time.
 Clock skew results because of different clock domains.
 Clock skew results because of an unbalanced clock tree.

3-38 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clocks: Minimizing Clock Skew
 Minimize clock skew during shift.
 Order scan chains:
– Group flip-flops together into one clock domain.
– Insert lockup latches where domains cross.

Combinational
CombinationalLogic
Logic

SO
D Q D Q D Q D Q D Q
SI
SI SI LL1 SI SI
A B EN
C D
Clk1
Clk2

Multiple Clocks
Inserted
Lockup Latch

3-39 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clocks
design.v dft.lib

DFTAdvisor
 By default all clock primary inputs
Non-scan DFT Library
Netlist

Setup
and edges are placed in separate
Scan/Test Logic
Configuration
scan chains.
Design Rule
Checking
Scan
DFT> INSert TEst Logic
Identification
Scan/Test Logic
Insertion
Scan In 1
Write Results CLK 1 Scan Out 1

Scan In 2
Scan Out 2

Scan Inserted ATPG Dofile Test

Netlist Procedure File

Scan In 3 Scan Out 3

CLK 2

3-40 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clocks: Merging Clock Edges
 Leading and trailing edge clocks can be combined into the
same scan chain.
 DFTAdvisor groups all trailing edge clock scan cells first.

DFT> INSert TEst Logic -Edge Merge

LE
CLK 1 Scan Out 1

Scan In 1

TE
Scan In 2
Scan Out 2
CLK 2

3-41 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clocks: Merging Different Clocks

 Different clocks can be merged into the same chain.

 DFTAdvisor selects scan cells to be merged.
 Tessent DFTAdvisor places lockup latches between each
clock domain.
DFT> SET LOckup Cell on
DFT> INSert TEst Logic -clock merge
 Multiple clocks can be combined into ‘clock
groups’.
 Explicitly defines which clocks can be placed into the
same scan chain.
DFT> ADD CLocks 0 clk1 clk2 clk3
DFT> ADD CLock Groups group1 clk1 clk2 clk3
DFT> SET LOckup Cell on
DFT> INSert TEst Logic -clock merge

3-42 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Multiple Clocks: Using Lockup Latches
design.v dft.lib

DFTAdvisor
Non-scan DFT Library
Netlist
 Insert lockup latch.
Setup

Scan/Test Logic SETUP> ADD CLocks 0 clk1 clk2

Configuration

Design Rule
Checking SETUP> SET System Mode dft
Scan
Identification
Scan/Test Logic DFT> ADD CLock Groups grp1
Insertion
clk1 clk2
Write Results
DFT> ADD CEll Model DLat1
-Type DLat enable data
-Active Low
ATPG DFT> SET LOckup Cell ON –Type DLat
Scan Inserted Dofile Test .
Netlist Procedure File .
.
Scan In 2 DFT> INSert TEst Logic -Clock
CLK 1
D Q
Merge
grp 1
EN DFT> REPort TEst Logic
Scan In 1 Scan Out 1

Scan Out 2
CLK 2
grp 1

DFT> INSert TEst Logic -Clock Merge

3-43 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Balancing Scan Chains
 Testers need deep serial
memory for every scan
input and output pin.
 Functional pins can be
shared as scan pins in test
mode.
 Test time and cost is
reduced with more and
shorter scan chains.
 The number of scan chains
is dependent upon tester
capabilities.

3-44 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Balancing Scan Chains (Cont.)
design.v dft.lib

DFTAdvisor
Non-scan DFT Library
Netlist
Setup
 Balance scan chains by defining their
Scan/Test Logic maximum length or by setting their
Configuration
Design Rule
total number.
Checking
Scan
Identification
Scan/Test Logic SETUP> ADD CEll Models DLat1 –Type \
Insertion

Write Results
DLat enable data -Active Low
SETUP> SET LOckup Cell ON –Type DLat
DFT> INSert TEst Logic -Clock Merge \
-Edge Merge -NUmber 5
Scan Inserted ATPG Test
Netlist Dofile Procedure File

Scan In 1 Scan Out 1

Scan In 2 Scan Out 2

5 scan chains will be balanced
Scan In 3 Scan Out 3 automatically.

Scan In 4 Scan Out 4

Scan In 5 Scan Out 5

Scan Enable

3-45 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Chain Ordering and Stitching
 Mux-scan designs:
 Scan cells must be correctly ordered to prevent skew during
shift.
 Better placement and routing of scan cells results in better
stitching.
 To optimize a scan design layout:
 Remove all previous scan chains from the design.
 Reorder the scan cells and write a scan cell order file.
 Stitch scan cells into scan chains using the scan cell order file.

3-46 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Chain Ordering and Stitching Flow
design.v dft.lib

Non-scan DFTAdvisor DFT Library

Dofile
Netlist

Setup .
.
Scan/Test Logic .
Configuration
SETUP> SET SYstem Mode DFT
Design Rule
Checking DFT> RIPup SCan Chains -All
Scan
Identification DFT> RUN
Scan/Test Logic DFT> INSert TEst Logic \
Insertion
order.txt -
Write Results
fixed

Scan Inserted ATPG Test

Netlist Dofile Procedure File

Placement
and Routing Scan Chain
Order File
order.txt

Before Reordering After Reordering

Scan In 1 Scan In 1
U1 U8 U5 U2 U8 U1 U5 U2
CLK 2 Scan Out 1 CLK 2 Scan Out 1

3-47 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Cell Configuration After Ripup

TIED

D Q
D Q

CLK
Loop
CLK
Scan_en Scan_en

D Q

Scan_en Buffer
CLK

3-48 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Chain Stitching: Stitching Existing Scan Cells
 When stitching existing scan, define the following:
 Scan enable (If, previously connected).
SETUP> SET SCan Enable
 The “data_in” field of the DFT library model.

model sff
model sff (D, SI, SE, CLK, Q, QB) (
scan_definition (
type = mux_scan;
data_in
data_in = D; D IN0
scan_in = SI; _D Q
scan_enable = SE; Q
scan_out = Q, QB; IN1 _D
SI
non_scan_model = dff (D, CLK, Q, QB);
) SE
input (D, SI, SE, CLK) ( )
intern(_D) (primitive = _mux (D, SI, SE, _D);) _mux QB QB
output(Q, QB) (primitive = _dff(, , CLK, _D, Q, QB);) SE
_dff
CLK

3-49 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation
 Lab 3: Configuring Scan Chains/Test Logic
During this lab, you will

 Configure scan chains and insert test logic in a full scan flow.
 Set up scan pins
 Balance scan chains with multiple domains
 Stitch scan chains

3-50 • Tessent: Scan and ATPG: Scan Insertion and Configuration Copyright © 1999-2009 Mentor Graphics Corporation