Unit 6 : Basic Processing

By S. R. Milke
Hardwired and Microprogrammed Control
Unit
• Control Unit is responsible for controlling all operations by sending
control signals.
• A control Unit can be implemented by two techniques
a) Hardwired Control Unit
b) Micro programmed Control Unit

• Hardwired Control unit is implemented as a sequential logic circuit or

a finite state machine that generates a specific sequence of control
signals.
• Two decoders, sequence counter and logic gates make up a Hardwired
Control.
• The instruction register stores an instruction retrieved from the memory
unit (IR).
• An instruction register consists of the operation code, the I bit, and bits 0
through 11.
• A 3 x 8 decoder is used to encode the operation code in bits 12 through
14.
• The decoder’s outputs are denoted by the letters D0 through D7.
• The bit 15 operation code is transferred to a flip-flop with the symbol I.
• The control logic gates are programmed with operation codes from bits 0
to 11.
• The sequence counter (or SC) can count from 0 to 15 in binary.
• There are four techniques for design of hardwired control unit
1) State Table method
• Classical method of sequential design
• Minimizes hardware
• Constructs a state transition table
• Every generation of states has a set of control signals
2) Delay element method
• Control signals follow a proper sequence
• A specific time delay between two groups of control signals
• TO ensure synchronization D-flip flops are controlled by a common
clock signals
3) Sequence Counter method
• It uses counter for timing purposes
4) PLA method
• It uses programmable logic array.
• PLA is logic device containing programmable AND gates followed by
programmable OR gates, while ROM has fixed AND gates and
programmable OR gates.
• PLA can be used as Decoder, Counter and BUS interface also.
Microprogrammed control unit

• In microprogrammed control unit micro instructions are stored in a

special memory called control memory
• Implemented using programming approach
• Sequences is carried out by executing a program consisting of micro
instructions
• The microinstruction address is specified in the control memory address
register.
• All the control information is saved in the control memory, which is
considered to be a ROM.
• The microinstruction received from memory is stored in the control
register.
• A control word in the microinstruction specifies one or multiple micro-
operations for a data processor.
• The next address is calculated in the circuit of the next address generator
and then transferred to the control address register for reading the next
microinstruction when the micro-operations are being executed.
• Because it determines the sequence of addresses received from control
memory, the next address generator is also known as a microprogram
sequencer.
• Advantages :
1. Micro program can be changed easily
2. Flexible ( code reusability)
3. Better in terms of scalability than hard wired ( can expand code)

• Disadvantages:
1. Hardware cost is more because of control memory and its access
circuitry
2. Slower than hardwired
Hardwired Control Unit Microprogrammed Control Unit

Hardwired control unit generates the control signals needed Micro programmed control unit generates the control signals
for the processor using logic circuits with the help of micro instructions stored in control memory

Hardwired control unit is faster when compared to This is slower than the other as micro instructions are used
microprogrammed control unit as the required control for generating signals here
signals are generated with the help of hardware

Difficult to modify as the control signals that need to be Easy to modify as the modification need to be done only at
generated are hard wired the instruction level

More costlier as everything has to be realized in terms of Less costlier than hardwired control as only micro
logic gates instructions are used for generating control signals

It cannot handle complex instructions as the circuit design It can handle complex instructions
for it becomes complex

Only limited number of instructions are used due to the

hardware implementation Control signals for many instructions can be generated

Used in computer that makes use of Reduced Instruction Set Used in computer that makes use of Complex Instruction Set
Computers(RISC) Computers(CISC)
S. No Horizontal µ-programmed CU Vertical µ-programmed CU

1. It supports longer control word. It supports shorter control word.

It allows a higher degree of parallelism. If degree is n, then It allows a low degree of parallelism i.e., the degree of
2. n Control Signals are enabled at a time. parallelism is either 0 or 1.

Additional hardware in the form of decoders is required to

3. No additional hardware is required. generate control signals.

4. It is faster than a Vertical micro-programmed control unit. it is slower than a Horizontal micro-programmed control unit.

It is less flexible than a Vertical micro-programmed control It is more flexible than a Horizontal micro-programmed control
5. unit. unit.

A vertical micro-programmed control unit uses vertical micro-

A horizontal micro-programmed control unit uses horizontal instruction, where a code is used for each action to be performed
micro-instruction, where every bit in the control field and the decoder translates this code into individual control
6. attaches to a control line. signals.

The horizontal micro-programmed control unit makes less

use of ROM encoding than the vertical micro-programmed The vertical micro-programmed control unit makes more use of
7. control unit. ROM encoding to reduce the length of the control word.
Parallelism
• Computer architects are constantly striving to improve performance
of the machines they design.
• Making the chips run faster by increasing their clock speed is one way,
However, most computer architects look to parallelism (doing two or
more things at once) as a way to get even more performance for a
given clock speed.
• Parallelism comes in two general forms: –
1) instruction-level parallelism, and
2) processor-level parallelism.
Instruction-Level Parallelism
• Parallelism is exploited within individual instructions to get more
instructions/sec out of the machine.
• We will consider two approached
– Pipelining
– Superscalar Architectures
Pipelining
• Fetching of instructions from memory is a major bottleneck in instruction
execution speed. However, computers have the ability to fetch instructions
from memory in advance .
• These instructions were stored in a set of registers called the prefetch
buffer.
• Thus, instruction execution is divided into two parts: fetching and actual
execution;
• The concept of a pipeline carries this strategy much further.
• Instead of dividing instruction execution into only two parts, it is often
divided into many parts, each one handled by a dedicated piece of
hardware, all of which can run in parallel.
Dual Pipelines
• If one pipeline is good, then surely two pipelines are better.
• Here a single instruction fetch unit fetches pairs of instructions
together and puts each one into its own pipeline, complete with its
own ALU for parallel operation.
• To be able to run in parallel, the two instructions must not conflict
over resource usage (e.g., registers), and neither must depend on the
result of the other.
Superscalar Architectures
• Going to four pipelines is conceivable, but doing so duplicates too
much hardware
• Instead, a different approach is used on highend CPUs.
• The basic idea is to have just a single pipeline but give it multiple
functional units.
• This is a superscalar architecture – using more than one ALU, so that
more than one instruction can be executed in parallel.
• Implicit in the idea of a superscalar processor is that the S3 stage can
issue instructions considerably faster than the S4 stage is able to
execute them.
Processor-Level Parallelism
• Instruction-level parallelism (pipelining and superscalar operation)
rarely win more than a factor of five or ten in processor speed.
• To get gains of 50, 100, or more, the only way is to design computers
with multiple CPUS
• We will consider three alternative architectures: –
• Array Computers
• Multiprocessors
• Multicomputers
Array Computers
• An array processor consists of a large number of identical processors
that perform the same sequence of instructions on different sets of
data.
• A vector processor is efficient at executing a sequence of operations
on pairs of Data elements; all of the addition operations are
performed in a single, heavily-pipelined adder.
Multiprocessors
• The processing elements in an array processor are not independent
CPUS, since there is only one control unit.
• The first parallel system with multiple full-blown CPUs is the
multiprocessor.
• This is a system with more than one CPU sharing a common memory
co-ordinated in software.
• The simplest one is to have a single bus with multiple CPUs and one
memory all plugged into it.
Multicomputers
• Although multiprocessors with a small number of processors (< 64)
are relatively easy to build, large ones are surprisingly difficult to
construct.
• The difficulty is in connecting all the processors to the memory.
• To get around these problems, many designers have simply
abandoned the idea of having a shared memory and just build
systems consisting of large numbers of interconnected computers,
each having its own private memory, but no common memory.
• These systems are called multicomputers.