Module 5- Accessing I/O devices

Part 1- Accessing I/O, Interrupts, DMA

Dr. Ilavarasi A K, VIT Chennai

 Accessing I/O Devices
• Simple arrangement to connect I/O devices to a computer – single bus
• Enables all devices connected to it to exchange information
• Consists of three sets of lines – control,address, data
• Each device is assigned a unique set of addresses.
• The memory and the I/O devices may share the same address space (memory-
mapped I/O) or may be have separate spaces.
• Same address space  any instruction that can access the memory can
be
used to access I/O devices as well (e.g.: Move DATAIN, R0)
• Simpler software
• Different address space  special In and Out instructions for I/O transfers
• Second approach – I/O devices deal with fewer address lines
Dr. Ilavarasi A K, VIT Chennai
Accessing I/O Devices Data register holds
data
• When the processor places being transferred
particular
a address on
the address lines, the
device that this address
recognizes
responds the commands
(read/write)
to sent over the
command lines.
• Data is over
transferred data the
lines.
• I/O interface
decoder, control circuits,
– Enables device to
Status register contains
unit
data and status registers
address recognize the
information relevant
address
to the I/O operation
Dr. Ilavarasi A K, VIT Chennai
Accessing I/O Devices
• Methods for communicating with I/O devices/implementing I/O operations:
• Program-controlled I/O
• Processorவாத்தி repeatedly checks a status flag (e.g.: SIN or SOUT) to
achieve synchronization(mingle) with I/O device. – Polling
• Interrupts
• Involves the I/O device(student) sending a special signal to processor
over the bus whenever it is ready for data transfer
• Direct memory access (DMA)
• Used for high-speed I/O devices
• Involves continuous data transfer without involvement of the processor

• Signal laam anupi permission keka maatan,venum na transfer

Dr. Ilavarasi A K, VIT Chennai
 Interrupts
• In program-controlled I/O, the processor is put through a waiting period, where
Io :-Doubt
it constantly tests the device status and does not perform any useful task.
keke ready • To allow the processor to perform some other task till the I/O device is ready,
ah!
the
I/O device could alert the processor when ready
• Can be accomplished by sending a hardware signal called interrupt
• One of the bus control lines allotted for this – interrupt-request line
• Processor need not continuously check the status of the I/O devices.
• Waiting periods eliminated
• Routine executed in response to an interrupt – Interrupt Service Routine (ISR)

Dr. Ilavarasi A K, VIT Chennai

Interrupt - Example
COMPUTE routine PRINT
routine

1
2 .
.
. .
.
Interrup i .
t
i+1 .
.
.
M

Dr. Ilavarasi A K, VIT Chennai

Handling Interrupts
• Once an interrupt request is received, the processor must stop executing the
current program and execute an interrupt service routine (PRINT routine in
the example).
• If the interrupt request is received when the ith instruction is being executed,
the processor does the following:
• It first completes the execution of the ith instruction.
• It stores the current contents of the PC in a special register (Link
register)or a stack.
• It loads the PC with the address of the first instruction of the ISR.
• After the ISR has finished executing, the return-from-interrupt signal at the
end
of the ISR reloads the previous content of the PC from the temporary
storage.
Dr. Ilavarasi A K, VIT Chennai
 Handling Interrupts
• Apart from storing the contents of the PC, condition codes and contents of
registers used by both the interrupted program and the ISR may be saved and
restored.
• Task of saving and restoring can be done automatically by the processor or by
program instructions.
• The process of saving and restoring is time-consuming (involves memory
transfers)  Most modern processors only save and restore the bare
minimum, typically PC and status register.
• Remaining information if required can be saved by program instructions
at the
beginning of the ISR.
• Time between when an interrupt request is received and ISR execution
starts –
interrupt latency Dr. Ilavarasi A K, VIT Chennai
Enabling and Disabling Interrupts
• Programmer must be able to control the events that take place during program
execution.
• Arrival of interrupts may alter the sequence envisaged by the programmer.
• Therefore, there is a facility to enable and disable interrupts as desired.
• Processor might have to ignore interrupts in certain cases.
• Examples:
• In the Compute-Print example, interrupt request from the printer
should only be accepted if there is content to be printed.
• The ISR may change data used by a program being executed, in which case a
particular sequence of instructions must be executed without interruption.

Dr. Ilavarasi A K, VIT Chennai

Enabling and Disabling Interrupts
• When a device activates the interrupt-request signal, it keeps this signal
activated, till it learns that the processor has accepted its request.
• It is essential to ensure that the active request signal is not interpreted as successive
interruptions.
• Three ways for the processor to handle the above:
• Ignore handling Until ISR Starts:
• What Happens: The processor delays handling the interrupt until the Interrupt Service Routine (ISR) begins.
• How: At the start of ISR, interrupts are disabled, ensuring no interruption. At the end, interrupts are re-enabled, allowing new
interrupt requests.
• Save and Disable:
• What Happens: The processor saves its current state, disables interrupts, executes the ISR, and then restores the saved state.
• How: The interrupt flag is disabled before the ISR starts, preventing additional interrupts. It's re-enabled during the restoration
process.
• Edge-Triggered Handling:
• What Happens: The interrupt circuit only responds to the initial change in the signal, ignoring subsequent changes until it returns
to its initial state.
Dr. Ilavarasi A K, VIT Chennai
• How: Ensures that a single change in the signal triggers the interrupt, avoiding multiple interpretations for a continuous signal.
Interrupt Handling – Summarized
• Sequence of steps involved in handling interrupt from a single device:
ung
al re
• The device raises an interrupt request. vetr quest
a pa n
dum irai
• The processor interrupts the program currently being executed.
• PC and status register contents are stored.
• Interrupts are disabled. device

• Device is informed that its request has been recognized.

• Device deactivates interrupt request signal.
• Action requested is performed by the interrupt service routine.
• Interrupts are enabled, PC and status register are restored, and
interrupted
program is resumed.
Dr. Ilavarasi A K, VIT Chennai
Handling Multiple Devices
• How can the processor recognize the device requesting an interrupt?

• How will it know the starting address of the interrupt service

routine?

• Can a second device interrupt while the first is being serviced?

• How should simultaneous interrupt requests be handled?

Dr. Ilavarasi A K, VIT Chennai

Vectored Interrupts
• How can the processor recognize the device requesting an
interrupt?
• How will it know the starting address of the interrupt service
routine?
• Polling all the devices – Time consuming
• Vectored Interrupts
• Device requesting interrupt should identify itself.
• Should send a special code, which can also represent the
address of the interrupt service routine
• Code length – typically 4 to 8 bits, remaining bits
identified by the processor Dr. Ilavarasi A K, VIT Chennai
Interrupt Nesting
• Can a second device interrupt while the first is being serviced?
• Interrupts can be disabled when one interrupt is being serviced. However,
certain interrupt requests may have to be attended to immediately. (E.g.:
real- time clock)
• Assign priority
• A priority level can be assigned to the processor, which will be priority
level of the program currently being executed.
• Interrupt-request from a high-priority device should be accepted when
the processor is servicing another request from a lower-priority device.
• This will disable interrupts from devices that have the same or lower
priority.

Dr. Ilavarasi A K, VIT Chennai

Interrupt Nesting

Dr. Ilavarasi A K, VIT Chennai

Simultaneous Requests
• How should simultaneous interrupt requests be handled?
• Priority can be assigned, or polling can be used
• Connect interrupt acknowledge line in a daisy-chain fashion
• Devices share a common interrupt-request line (INTR).
•Interrupt acknowledgement propagates serially through devices using an interrupt
acknowledge line (INTA).
• If a device requires no service, it passes the signal to the next device in the
chain. If it needs service, it blocks the signal, preventing it from reaching
subsequent devices

Service thevai? Dr. Ilavarasi A K, VIT Chennai

Handling Multiple Devices
Priority Groups – Combination of the last two
methods

Dr. Ilavarasi A K, VIT Chennai

 Direct Memory Access
• Transfer of input/output data happens only after I/O device is ready.
• Processor polls or waits for an interrupt.
• Considerable overhead incurred when a block of data is to be transferred
• Solution:
• Special control unit to allow transfer of a block of data between
main
 memory and external device without processor intervention
• Direct Memory Access (DMA)
• A control circuit residing in the I/O device, managing the data transfer
process.
• Operation must be under the control of a program executed by the processor.
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Use of DMA Controller

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Sequence of Steps
• To initiate transfer, processor sends starting address, number of
words in the block, and direction of transfer.
• Starting address and word count are placed in the appropriate
registers.
• The control and status register signals the direction of transfer (read or
write).
• Processor puts the program that requested
transfer in blocked state and executes another
program.
• DMA controller performs the required process and sends an interrupt
signal on completion.
• Once a block of data has been transferred, controller sets “Done” to 1.
• When IE = 1, controller raises an interrupt after the transfer of a
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block. Dr. Ilavarasi A K, VIT Chennai
Cycle Stealing and Burst Mode
• Memory can be access by both processor and DMA controllers
• Requests from DMA controller are given higher priority than processor requests.
• Among different DMA devices, top priority is given to high-speed peripherals.
• Since the processor originates most memory access cycles, the DMA(k)
controller can be said to steal memory cycles from processor – Cycle stealing
• DMA controller may also be given exclusive access to the main memory
without any interruption – Block or burst mode
• A conflict may arise if both the processor and a DMA controller or two
DMA controllers attempt to use the bus at the same time to access the main
memory.
• To resolve these conflicts, an arbitration procedure is implemented.
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Bus Arbitration
• Device allowed to initiate data transfers on the bus at any given time
bus master
• When the current master relinquishes control of the bus, another
device can acquire the status.
• Bus arbitration–The process of selecting the next bus master and transferring
bus control to that device.
• Two approaches to bus arbitration:
• Centralized – Single bus arbiter performs the arbitration
• Distributed – All devices participate in the process of selection

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Dr. Ilavarasi A K, VIT Chennai
Centralized Arbitration
• The bus arbiter may be the processor, or a separate unit connected to the
bus.
• A simple arrangement for bus arbitration using a daisy chain:

Bus-busy line

Bus-request line

Bus-grant

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Centralized Arbitration
• The processor will be the bus master till it grants mastership to one of the
DMA controllers.
• A DMA controller indicates that it needs to become bus master by sending out a
bus-request signal (𝐵𝑅).
• The processor then sends out the bus-grant signal (𝐵𝐺 ) in a daisy-
chain arrangement.
• The DMA controller that requested to be bus master accepts the bus-
grant signal, waits for the bus-busy line (𝐵𝐵𝑆𝑌) to become inactive and
then assumes mastership of the bus.
• This DMA controller also activates the 𝐵𝐵𝑆𝑌 line again to
keep other DMA controllers from accessing the bus.

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Centralized Arbitration
• Multiple DMA controllers may send out a bus-request signal at a time.
• The signal on the 𝐵𝑅 line is an OR of all the bus-request signals.
• First DMA controller on the daisy-chain gets granted the bus mastership.
• The devices can also be arranged in priority groups.
• The arbiter ensures that only one request is granted at a time,
based on
priority – 𝐵𝑅1 with the highest priority and 𝐵𝑅𝑝 with the lowest
• Rotating priority scheme could also be used.
• If 𝐵𝑅1 is granted first, then the priority becomes 2, 3, … , p, 1

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Centralized Arbitration

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Dr. Ilavarasi A K, VIT Chennai
Distributed Arbitration
1. Equal Responsibility:
1. All devices waiting to use the bus have equal responsibility in the arbitration process. No central
arbiter is present
Each device on the bus is assigned a unique 4-bit identification number
When devices want to use the bus, they assert the Start − arbitration signal.
And They place their ID numbers on the ID lines.
Determining Priority:
2. The code on the ID lines represents the request with the highest ID number.
3. In the example, devices A (0101) and B (0110) contend for the bus, and B, with a higher ID, gets
priority
 Distributed Arbitration
• A transmits 0101 and B transmits 0110.
• The connection performs an OR operation,
so the code seen by the two devices will be
0111.
• Each device compares the pattern on the
arbitration lines to its own ID, starting from
the most significant bit.
• If it detects a difference at any bit position,
it disables drivers (makes the value 0) at
that bit position and all lower bits.
• This will ultimately cause the arbitration
lines to reflect the highest ID, namely, 0110.
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Dr. Ilavarasi A K, VIT Chennai