Main Memory

Background

 Program must be brought (from disk) into memory

and placed within a process for it to be run
 Main memory and registers are only storage CPU can
access directly
 Register access in one CPU clock (or less)
 Main memory can take many cycles
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct
operation
 Base and Limit Registers
 A pair of base and limit registers define the logical
address space
 Binding of Instructions and Data to
Memory

 Address binding of instructions and data to memory

addresses can happen at three different stages
 Compile time: If memory location known a
priori, absolute code can be generated; must
recompile code if starting location changes
 Load time: Must generate relocatable code if
memory location is not known at compile time
 Execution time: Binding delayed until run time
if the process can be moved during its
execution from one memory segment to
another. Need hardware support for address
maps (e.g., base and limit registers)
Multistep Processing of a User Program
Logical vs. Physical Address Space

 An address generated by the CPU is commonly referred to as

a logical address, whereas an address seen by the memory
unit—that is, the one loaded into the memory-address register
of the memory—is commonly referred to as a physical
address.
 The compile-time and load-time address-binding methods
generate identical logical and physical addresses.
 However, the execution-time address binding scheme results
in differing logical and physical addresses. In this case, we
usually refer to the logical address as a virtual address.
 The set of all logical addresses generated by a program is a
logical address space; the set of all physical addresses
corresponding to these logical addresses is a physical
address space.
 Thus, in the execution-time address-binding scheme, the
logical and physical address spaces differ.
 Memory-Management Unit (MMU)

 The run-time mapping from virtual to physical addresses is

done by a hardware device called the memory-management
unit (MMU). We can choose from many different methods to
accomplish such mapping
 In MMU scheme, the value in the relocation register is added
to every address generated by a user process at the time it is
sent to memory

 The user program deals with logical addresses. The memory-

mapping hardware converts logical addresses into physical
addresses.
 We now have two different types of addresses: logical
addresses and physical addresses.
 The user program supplies logical addresses; these logical
addresses must be mapped to physical addresses before they
are used.
Dynamic relocation using a relocation
register
 Dynamic Loading

 The entire program and all data of a process must be in

physical memory for the process to execute.
 To obtain better memory-space utilization, we can use
dynamic loading.
 With dynamic loading, a routine is not loaded until it is called.
All routines are kept on disk in a relocatable load format.
 The main program is loaded into memory and is executed.
When a routine needs to call another routine, the calling
routine first checks to see whether the other routine has been
loaded.
 If not, the relocatable linking loader is called to load the
desired routine into memory and to update the program's
address tables to reflect this change. Then control is passed
to the newly loaded routine.
 The advantage of dynamic loading is that an unused routine is
never loaded.
 Swapping
 A process can be swapped temporarily out of memory to a backing store,
and then brought back into memory for continued execution

 Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these memory
images

 Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed

 Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped

 System maintains a ready queue of ready-to-run processes which have

memory images on disk
 Whenever the CPU scheduler decides to execute a process, it calls the
dispatcher.
 The dispatcher checks to see whether the next process in the queue is in
memory. If it is not, and if there is no free memory region, the dispatcher
swaps out a process currently in memory and swaps in the desired
process.
Schematic View of Swapping
 Contiguous Allocation

 Main memory usually into two partitions:

 Resident operating system, usually held in low
memory
 User processes then held in high memory

 Relocation registers used to protect user

processes from each other, and from changing
operating-system code and data
 Base register contains value of smallest
physical address
 Limit register contains range of logical
addresses – each logical address must be less
than the limit register
 MMU maps logical address dynamically
HW address protection with base and limit registers
 Partition

 One of the simplest methods for allocating memory is to divide

memory into several fixed-sized partitions.
 Each partition may contain exactly one process. Thus, the degree
of multiprogramming is bound by the number of partitions.
 In this multiple partition method, when a partition is free, a
process is selected from the input queue and is loaded into the free
partition.
 When the process terminates, the partition becomes available for
another process.
 In the fixed-partition scheme, the operating system keeps a table
indicating which parts of memory are available and which are
occupied. Initially, all memory is available for user processes and
is considered one large block of available memory, a hole.
 When a process arrives and needs memory, we search for a hole
large enough for this process. If we find one, we allocate only as
much memory as is needed, keeping the rest available to satisfy
future requests.
 Partition

 In general, at any given time we have a set of holes of various

sizes scattered throughout memory.
 When a process arrives and needs memory, the system searches
the set for a hole that is large enough for this process.
 If the hole is too large, it is split into two parts. One part is
allocated to the arriving process; the other is returned to the set of
holes.
 When a process terminates, it releases its block of memory, which
is then placed back in the set of holes.
 If the new hole is adjacent to other holes, these adjacent holes are
merged to form one larger hole.
 This procedure is a particular instance of the general dynamic
storage allocation problem, which concerns how to satisfy a
request of size n from a list of free holes.
 There are many solutions to this problem. The first-fit, best-fit, and
worst-fit strategies are the ones most commonly used to select a
free hole from the set of available holes.
 OS OS OS OS
process process process process
5 5 5 5
process process
9 9
process process
8 10

process process process process

2 2 2 2
 Dynamic Storage-Allocation
Problem

How to satisfy a request of size n from a list of free holes

 First-fit: Allocate the first hole that is big enough
 Best-fit: Allocate the smallest hole that is big
enough; must search entire list, unless ordered by
size
 Produces the smallest leftover hole
 Worst-fit: Allocate the largest hole; must also search
entire list
 Produces the largest leftover hole

First-fit and best-fit better than worst-fit in

terms of speed and storage utilization
 Fragmentation

 Both the first-fit and best-fit strategies for memory

allocation suffer from external fragmentation.
 As processes are loaded and removed from memory, the
free memory space is broken into little pieces.
 External fragmentation exists when there is enough total
memory space to satisfy a request, but the available
spaces are not contiguous; storage is fragmented into a
large number of small holes.
 In the worst case, we could have a block of free (or
wasted) memory between every two processes. If all these
small pieces of memory were in one big free block instead,
we might be able to run several more processes.
 Fragmentation

 Memory fragmentation can be internal as well as external. Consider

a multiple-partition allocation scheme with a hole of 18,464 bytes.
Suppose that the next process requests 18,462 bytes. If we
allocate exactly the requested block, we are left with a hole of 2
bytes. The overhead to keep track of this hole will be substantially
larger than the hole itself.
 The general approach to avoiding this problem is to break the
physical memory into fixed-sized blocks and allocate memory in
units based on block size.
 With this approach, the memory allocated to a process may be
slightly larger than the requested memory. The difference between
these two numbers is internal fragmentation
 Reduce external fragmentation by compaction
 Shuffle memory contents to place all free memory together in
one large block
 Compaction is possible only if relocation is dynamic, and is done
at execution time
 Paging

 The basic method for implementing paging involves

breaking physical memory into fixed-sized blocks called
frames and breaking logical memory into blocks of the
same size called pages.
 When a process is to be executed, its pages are loaded
into any available memory frames from the backing store.
 The backing store is divided into fixed-sized blocks that
are of the same size as the memory frames.
 Keep track of all free frames
 To run a program of size n pages, need to find n free
frames and load program
 Set up a page table to translate logical to physical
addresses
 Address Translation Scheme

 Address generated by CPU is divided into:

 Page number (p) – used as an index into a page

table which contains base address of each page in
physical memory

 Page offset (d) – combined with base address to

define the physical memory address that is sent to
pageunit
the memory number page offset

p d
m-n n

 For given logical address space 2m and page size 2n

Paging Hardware
Paging Model of Logical and Physical
Memory
 Paging Example

32-byte memory and 4-byte

pages
 Free Frames

Before allocation After allocation

Typical page table entry
 Implementation of Page Table

 Page table is kept in main memory

 Page-table base register (PTBR) points to the page
table
 Page-table length register (PRLR) indicates size of
the page table
 In this scheme every data/instruction access
requires two memory accesses. One for the page
table and one for the data/instruction.
 The two memory access problem can be solved by
the use of a special fast-lookup hardware cache
called associative memory or translation look-aside
buffers (TLBs)
 Some TLBs store address-space identifiers (ASIDs)
in each TLB entry – uniquely identifies each process
to provide address-space protection for that process
 Associative Memory

 Associative memory – parallel search

Page # Frame #

Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in memory
Paging Hardware With TLB
 Memory Protection

 Memory protection implemented by associating

protection bit with each frame

 Valid-invalid bit attached to each entry in the

page table:
 “valid” indicates that the associated page is in
the process’ logical address space, and is thus
a legal page
 “invalid” indicates that the page is not in the
process’ logical address space
Valid (v) or Invalid (i) Bit In A Page
Table
 Shared Pages

 Shared code
 One copy of read-only (reentrant) code shared
among processes (i.e., text editors, compilers,
window systems).
 Shared code must appear in same location in
the logical address space of all processes

 Private code and data

 Each process keeps a separate copy of the
code and data
 The pages for the private code and data can
appear anywhere in the logical address space
Shared Pages Example
 Segmentation

 Segmentation is a memory-management scheme that

supports the user view of memory.
 A logical address space is a collection of segments.
 Each segment has a name and a length.
 The addresses specify both the segment name and the offset
within the segment.
 The user therefore specifies each address by two quantities:
a segment name and an offset.
 For simplicity of implementation, segments are numbered and
are referred to by a segment number, rather than by a
segment name. Tluis, a logical address consists of a two
tuple:
< segment-number, offset >.
 Normally, the user program is compiled, and the compiler
automatically constructs segments reflecting the input
program.
 Segmentation

 A program is a collection of segments. A segment is

a logical unit such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays
User’s View of a Program
Logical View of Segmentation

4
1

3 2
4

user space physical memory space

 Address Translation

 A logical address consists of two parts: a segment number,

s, and an offset into that segment, d.
 The segment number is used as an index to the segment
table. The offset d of the logical address must be between
0 and the segment limit.
 If it is not, we trap to the operating system (logical
addressing attempt beyond, end of segment).
 When an offset is legal, it is added to the segment base to
produce the address in physical memory of the desired
byte.
 The segment table is thus essentially an array of base-limit
register pairs.
Segmentation Architecture (Cont.)

 Protection
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges
 Protection bits associated with segments; code
sharing occurs at segment level
 Since segments vary in length, memory
allocation is a dynamic storage-allocation
problem
 A segmentation example is shown in the
following diagram
Segmentation Hardware
Example of Segmentation