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Samara University College of Engineering and Technology Computer Science

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50 views49 pages

Samara University College of Engineering and Technology Computer Science

Uploaded by

haileamalk12
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Samara University

College of Engineering and Technology


Computer Science
Microprocessor and Assembly Language(CoSc 3025)

Chapter 2
The Microprocessor and its Architecture
Outline

Internal microprocessor architecture


Real mode memory addressing
Intro to protected mode memory addressing
Memory paging
CHAPTER OBJECTIVES
Upon completion of this chapter, you will be able to:

1. Describe the function and purpose of each program-visible register in the 8086–
Core2 microprocessors, including the 64-bit extensions.
2. Detail the flag register and the purpose of each flag bit.
3. Describe how memory is accessed using real mode memory-addressing techniques.
4. Describe how memory is accessed using protected mode memory-addressing
techniques.
5. Describe how memory is accessed using the 64-bit flat memory model.
6. Describe the program-invisible registers found within the 80286 through Core2
microprocessors.
7. Detail the operation of the memory-paging mechanism.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE

– Before a program is written or any instruction


investigated, the internal configuration of the
microprocessor must be known

– This section of the chapter details the program-visible


internal architecture of the 8086–Core2 microprocessors

– In a multiple core microprocessor each core contains the


same programming model. The only difference is that
each core runs a separate task or thread simultaneously.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

The Programming Model


– The programming model of the 8086 through the Core2 is
considered to be program visible because its registers are
used during application programming and are specified by
the instructions.
– program invisible registers are not addressable directly
during applications programming, but may be used
indirectly during system programming
– Only the 80286 and above contain the program-invisible
registers used to control and operate the protected
memory system and other features of the microprocessor

– Note : See topic 2.2 and 2.3 about real mode and
protected mode respectively
FIGURE 1 The programming
model of the 8086 through the
Core2 microprocessor including
the 64-bit extensions.

 The shaded areas


in this illustration
represent registers
that are found in
early versions of
the 8086, 8088, or
80286
microprocessors
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

The Programming Model


– The 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and
DL and are referred to when an instruction is formed
using these two-letter designations. For example, an ADD
AL,AH instruction adds the 8-bit contents of AH to AL.
(Only AL changes due to this instruction.)
– The 16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI,
IP, FLAGS, CS, DS, ES, SS, FS, and GS.
– Note that the first 4 16 registers contain a pair of 8-bit
registers.
– For example, an ADD DX, CX instruction adds the 16-bit
contents of CX to DX. (Only DX changes due to this
instruction.)extensions
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Multipurpose Registers
RAX – RAX is referenced as a 64-bit register (RAX), a 32-bit
(accumulator) register (EAX), a 16-bit register (AX), or as either of two 8-
bit registers (AH and AL). Note that if an 8- or 16-bit
register is addressed, only that portion of the 32-bit register
changes without affecting the remaining bits.
– The accumulator is used for instructions such as
multiplication, division, and some of the adjustment
instructions.

RBX – RBX is addressable as RBX, EBX, BX, BH, or BL. The BX


register sometimes holds the offset address of a location in
(base index) the memory system in all versions of the microprocessor. In
the 80386 and above, EBX also can address memory data. In
the 64-bit Pentium 4 and Core2, RBX can also address
memory data.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Multipurpose Registers
RCX – RCX, which is addressable as RCX, ECX, CX, CH, or CL,
(count) is a general-purpose register that also holds the count for
various instructions
– Instructions that use a count are the repeated string
instructions (REP/REPE/REPNE); and shift, rotate, and
LOOP/LOOPD instructions.

RDX – RDX, which is addressable as RDX, EDX, DX, DH, or DL,


(data) is a (data) general-purpose register that holds a part of the
result from a multiplication or part of the dividend before a
division. In the 80386 and above, this register can also
address memory data.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Multipurpose Registers
RBP – RBP, which is addressable as RBP, EBP, or BP, points to a
(Base pointer) memory location in all versions of the microprocessor for
memory data transfers

RDI – RDI, which is addressable as RDI, EDI, or DI, often


(destination addresses string destination data for the string instructions.
index)

– RSI is used as RSI, ESI, or SI. The source index register


RSI often addresses source string data for the string instructions.
(source index) Like RDI, RSI also functions as a general-purpose register.
As a 16-bit register, it is addressed as SI; as a 32-bit register,
it is addressed as ESI; and as a 64-bit register, it is addressed
as RSI.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Multipurpose Registers
R8 through – These registers are only found in the Pentium 4 and Core2 if
R15 64-bit extensions are enabled. As mentioned, data in these
registers are addressed as 64-, 32-, 16-, or 8-bit sizes and are
of general purpose.
– Most applications will not use these registers until 64-bit
processors are common.
– Please note that the 8-bit portion is the rightmost 8-bit only;
bits 8 to 15 are not directly addressable as a byte.

FIGURE 2 The EFLAG


and FLAG register counts for
the entire 8086 and Pentium
microprocessor family.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
– The special-purpose registers include RIP, RSP, and
RFLAGS; and the segment registers include CS, DS, ES,
SS, FS, and GS.

RIP – RIP addresses the next instruction in a section of memory


defined as a code segment. This register is IP (16 bits) when
(instruction the microprocessor operates in the real mode and EIP (32
pointer) bits) when the 80386 and above operate in the protected
mode.

– RSP addresses an area of memory called the stack. The stack


RSP memory stores data through this pointer and is explained
(stack later in the text with the instructions that address stack data.
pointer) This register is referred to as SP if used as a 16-bit register
and ESP if referred to as a 32-bit register.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
 FLAGS – RFLAGS are special purpose registers which indicate the
condition of the microprocessor and control its operation.

– Carry holds the carry after addition or the borrow after


C (carry) subtraction. The carry flag also indicates error conditions, as
dictated by some programs and procedures. This is
especially true of the DOS function calls.

– Parity is a logic 0 for odd parity and a logic 1 for even


P (parity) parity. Parity is the count of ones in a number expressed as
even or odd.
– For example, if a number contains three binary one bits, it
has odd parity. If a number contains no one bits, it has even
parity.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
A (auxiliary – The auxiliary carry holds the carry (half-carry) after addition
carry) or the borrow after subtraction between bit positions 3 and 4
of the result..

Z (zero)) – The zero flag shows that the result of an arithmetic or logic
operation is zero. If Z=1 , the result is zero; if Z=0 , the
result is not zero. This may be confusing, but that is how
Intel decided to name this flag.

– The sign flag holds the arithmetic sign of the result after an
S (sign) arithmetic or logic instruction executes. If S=1 , the sign bit
(leftmost bit of a number) is set or negative; if S=0, the sign
bit is cleared or positive.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
T (trap) – The trap flag enables trapping through an on-chip debugging
feature. (A program is debugged to find an error or bug.) If
the T flag is enabled (1), the microprocessor interrupts the
flow of the program on conditions as indicated by the debug
registers and control registers. If the T flag is a logic 0, the
trapping (debugging) feature is disabled.
I (interrupt) – The interrupt flag controls the operation of the INTR
(interrupt request) input pin. If I=1, the INTR pin is enabled;
if I=0 , the INTR pin is disabled. The state of the I flag bit is
controlled by the STI (set I flag) and CLI (clear I flag)
instructions.
D (direction) – The direction flag selects either the increment or decrement
mode for the DI and/or SI registers during string
instructions. If , the registers are automatically decremented;
if , the registers are automatically incremented. The D flag is
set with the STD (set direction) and cleared with the CLD
(clear direction) instructions.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
O (overflow) – Overflows occur when signed numbers are added or
subtracted. An overflow indicates that the result has
exceeded the capacity of the machine. For example, if 7FH
(+127 ) is added—using an 8-bit addition—to 01H (+1 ), the
result is 80H (–128). This result represents an overflow
condition indicated by the overflow flag for signed addition.
For unsigned operations, the overflow flag is ignored.

– IOPL is used in protected mode operation to select the


IOPL (I/O privilege level for I/O devices. If the current privilege level
privilege is higher or more trusted than the IOPL, I/O executes
level) without hindrance. If the IOPL is lower than the current
privilege level, an interrupt occurs, causing execution to
suspend. Note that an IOPL of 00 is the highest or most
trusted and an IOPL of 11 is the lowest or least trusted.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
NT (nested task) – The nested task flag indicates that the current task is nested
within another task in protected mode operation. This flag is
set when the task is nested by software.

RF (resume) – The resume flag is used with debugging to control the


resumption of execution after the next instruction.\

– The VM flag bit selects virtual mode operation in a protected


VM
mode system.
(virtual mode)
– The alignment check flag bit activates if a word or
AC (alignment doubleword is (alignment check) addressed on a non-word
check) or non-doubleword boundary. Only the 80486SX
microprocessor contains the alignment check bit that is
primarily used by its companion numeric coprocessor, the
80487SX, for synchronization.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
VIF (virtual – The VIF is a copy of the interrupt flag bit available to the
Pentium Pentium 4 microprocessors.
interrupt)

VIP (Virtual – VIP provides information about a virtual mode interrupt for
the Pentium up to Pentium 4 microprocessors. This is used
interrupt
in multitasking environments to provide the operating
pending) system with virtual interrupt flags and interrupt pending
information

– The ID flag indicates that the Pentium–Pentium 4


ID microprocessors support the CPUID instruction. The CPUID
(identification) instruction provides the system with information about the
Pentium microprocessor, such as its version number and
manufacturer.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
 Segment – Additional registers, called segment registers, generate
memory addresses when combined with other registers in
Registers the microprocessor. There are either four or six segment
registers in various versions of the microprocessor.

CS (code) – The code segment is a section of memory that holds the code
(programs and procedures) used by the microprocessor. The
code segment register defines the starting address of the
section of memory holding code.

– The data segment is a section of memory that contains most


DS (data) data used by a program. Data are accessed in the data
segment by an offset address or the contents of other
registers that hold the offset address.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…

Special-Purpose Registers
ES (extra) – The extra segment is an additional data segment that is used
by some of the string instructions to hold destination data.

SS (stack) – The stack segment defines the area of memory used for the
stack.
– The stack entry point is determined by the stack segment and
stack pointer registers. The BP register also addresses data
within the stack segment.

FS and GS – The FS and GS segments are supplemental segment registers


available in the 80386–Core2 microprocessors to allow two
additional memory segments for access by programs.
2.2) REAL MODE MEMORY ADDRESSING

– The 80286 and above operate in either the real or protected mode.
Only the 8086 and 8088 operate exclusively in the real mode. In
the 64-bit operation mode of the Pentium 4 and Core2, there is no
real mode operation.
– This section of the text details the operation of the microprocessor
in the real mode.
– Real mode operation allows the microprocessor to address only the
first 1M byte of memory space—even if it is the Pentium 4 or
Core2 microprocessor. Note that the first 1M byte of memory is
called the real memory, conventional memory, or DOS memory
system.
2.2) REAL MODE MEMORY ADDRESSING…

Segments and Offsets


– A combination of a segment address and an offset address accesses
a memory location in the real mode.
– All real mode memory addresses must consist of a segment
address plus an offset address.
– The segment address, located within one of the segment
registers, defines the beginning address of any 64K-byte
memory segment.
– The offset address selects any location within the 64K
byte memory segment. Segments in the real mode always
have a length of 64K bytes.
2.2) REAL MODE MEMORY ADDRESSING…

Segments and Offsets


– In the real mode, each segment register is internally appended (affix)
with a 0H on its rightmost end
– A real mode segment of memory is 64K in length, once the
beginning address is known, the ending address is found by adding
FFFFH. For example, if a segment register contains 3000H, the
first address of the segment is 30000H, and the last address is
30000H +FFFFH or 3FFFFH.

Table 1 Example of real mode segment adressess


2.2) REAL MODE MEMORY ADDRESSING…

Segments and Offsets


– this shows a memory
segment beginning at
10000H, ending at
location 1FFFFH
• 64K bytes in length

– also shows how an offset


address, called a
displacement, of F000H
selects location
1F000H in the memory
Figure 3 The real mode memory-addressing scheme, using a segment address
plus an offset.
2.2) REAL MODE MEMORY ADDRESSING…
Default Segment and Offset Registers
– The microprocessor has a set of rules that apply to segments
whenever memory is addressed.
– These rules, which apply in the real and protected mode, define the
segment register and offset register combination.
– The code segment register is always used with the instruction
pointer to address the next instruction in a program.
– This combination is CS:IP or CS:EIP, depending upon the
microprocessor’s mode of operation.
– The code segment register defines the start of the code segment
and the instruction pointer locates the next instruction within the
code segment.
– This combination (CS:IP or CS:EIP) locates the next instruction
executed by the microprocessor. For example, if CS=1400H and
IP/EIP=1200H , the microprocessor fetches its next instruction
from memory location 14000H +1200H or 15200H.
2.2) REAL MODE MEMORY ADDRESSING…
Default Segment and Offset Registers
– Another of the default combinations is the stack. Stack data are
referenced through the stack segment at the memory location
addressed by either the stack pointer (SP/ESP) or the pointer
(BP/EBP). These combinations are referred to as SS:SP (SS:ESP),
or SS:BP (SS:EBP).
– For example, if SS=2000H and BP=3000H , the microprocessor
addresses memory location 23000H for the stack segment memory
location.

Table 2 Default 16-bit segment and offset combinations.


2.2) REAL MODE MEMORY ADDRESSING…
Default Segment and Offset Registers

Table 3 Default 32-bit segment and offset combinations.


2.2) REAL MODE MEMORY ADDRESSING…
Default Segment and Offset Registers
– think of segments as
windows that can be
moved over any area
of memory to access data
or code
– a program can have more
than four or six segments,
• but only access four or six segments
at a time

Figure 4 A memory system showing the


placement of four memory segments.
2.2) REAL MODE MEMORY ADDRESSING…
Default Segment and Offset Registers

Segment plus offset addressing allows DOS programs to be


relocated in memory.
A relocatable program is one that can be placed into any area of
memory and executed without change.
Relocatable data are data that can be placed in any area of
memory and used without any change to the program.
Because memory is addressed within a segment by an offset
address, the memory segment can be moved to any place in the
memory system without changing any of the offset addresses.
Only the contents of the segment register must be changed to
address the program in the new area of memory.
Windows programs are written assuming that the first 2G of
memory are available for code and data.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING

– Protected mode memory addressing (80286 and above) allows


access to data and programs located above the first 1M byte of
memory, as well as within the first 1M byte of memory
– Protected mode is where Windows operates.
– Addressing this extended section of the memory system requires a
change to the segment plus an offset addressing scheme used with
real mode memory addressing.
– When data and programs are addressed in extended memory, the
offset address is still used to access information located within the
memory segment.
– One difference is that the segment address, as discussed with real
mode memory addressing, is no longer present in the protected
mode.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING

– In place of the segment address, the segment register contains a


selector that selects a descriptor from a descriptor table. The
descriptor describes the memory segment’s location, length, and
access rights. Because the segment register and offset address still
access memory, protected mode instructions are identical to real
mode instructions
WHAT IS THE DIFFERENCE BETWEEN THE TWO
MODES?
– In fact, most programs written to function in the real mode will
function without change in the protected mode.
– The difference between modes is in the way that the segment
register is interpreted by the microprocessor to access the memory
segment.
– Another difference, in the 80386 and above, is that the offset
address can be a 32-bit number instead of a 16-bit number in the
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


– The selector, selects a descriptor from a descriptor table
– The descriptor describes the memory segment’s location, length,
and access rights.
– Indirectly, the segment register still selects a memory segment, but
not directly as in the real mode. For example, in the real mode, if
CS=0008H, the code segment begins at location 00080H.
– In the protected mode, this segment number can address any
memory location in the entire system for the code segment, as
explained shortly..
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


– There are two descriptor tables used with the segment registers:
one contains global descriptors and the other contains local
descriptors
– The global descriptors contain segment definitions that apply to
all programs, whereas the local descriptors are usually unique to
an application. You might call a global descriptor a system
descriptor and call a local descriptor an application descriptor.
– Each descriptor table contains 8192 descriptors, so a total of
16,384 total descriptors are available to an application at any time.
Because the descriptor describes a memory segment, this allows
up to 16,384 memory segments to be described for each
application.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


Figure 5 shows the format of a descriptor for the 80286 through the Core2.
each descriptor is 8 bytes in length
global and local descriptor tables are a maximum of 64K bytes in length

Figure 5 The 80286 through Core2 64-bit descriptors.


2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


The base address of the descriptor indicates the starting location of the memory segment.
the paragraph boundary limitation is removed in protected mode
segments may begin at any address
The G, or granularity bit allows a segment length of 4K to 4G bytes in steps of 4K bytes.
32-bit offset address allows segment lengths of 4G bytes
16-bit offset address allows segment lengths of 64K bytes.
Operating systems operate in a 16- or 32-bit environment.
DOS uses a 16-bit environment.
Most Windows applications use a 32-bit environment called WIN32.
MSDOS/PCDOS & Windows 3.1 operating systems require 16-bit instruction mode.
Instruction mode is accessible only in a protected mode system such as Windows Vista.
The access rights byte controls access to the protected mode segment.
describes segment function in the system and allows complete control over the segment
if the segment is a data segment, the direction of growth is specified
If the segment grows beyond its limit, the operating system is interrupted, indicating a
general protection fault
You can specify whether a data segment can be written or is write-protected.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


Figure 6 The access rights byte
for the 80286 through Core2
descriptor.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


Descriptors are chosen from the descriptor table by the segment
register.
register contains a 13-bit selector field, a table selector bit, and
requested privilege level field
The TI bit selects either the global or the local descriptor table.
Requested Privilege Level (RPL) requests the access privilege level
of a memory segment.
If privilege levels are violated, system normally indicates an
application or privilege level violation
.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors

Figure 7 The contents of a segment register during protected mode


operation of the 80286 through Core2 microprocessors.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors


Figure 8 shows how the segment register, containing a selector,
chooses a descriptor from the global descriptor table.
The entry in the global descriptor table selects a segment in the
memory system.
Descriptor zero is called the null descriptor, must contain all
zeros, and may not be used for accessing memory.
.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Selectors and Descriptors

Figure 8 Using the DS register to select a description from the global


descriptor table. In this example, the DS register accesses memory locations
00100000H–001000FFH as a data segment.
2.3) INTRODUCTION TO PROTECTED
MODE MEMORY ADDRESSING…

Program-Invisible Registers
– The global and local descriptor tables are found in the memory
system. In order to access and specify the address of these tables,
the 80286–Core2 contain program-invisible registers.
– The program-invisible registers are not directly addressed by
software so they are given this name (although some of these
registers are accessed by the system software).
– Figure 9 illustrates the program-invisible registers as they appear
in the 80286 through the Core2.
– These registers control the microprocessor when operated in
protected mode.
2.3) INTRODUCTION TO PROTECTED MODE
MEMORY ADDRESSING…
Program-Invisible Registers

FIGURE 9 The program-invisible register within the 80286–Core2 microprocessors.


2.4 MEMORY PAGING

– The memory paging mechanism located within the 80386 and


above allows any physical memory location to be assigned to any
linear address.
– The linear address is defined as the address generated by a
program.
– The physical address is the actual memory location accessed by a
program.
– With the memory paging unit, the linear address is invisibly
translated to any physical address, which allows an application
written to function at a specific address to be relocated through the
paging mechanism.
– It also allows memory to be placed into areas where no memory
exists. An example is the upper memory blocks provided by
EMM386.EXE in a DOS system.
2.4) MEMORY PAGING…

Paging Registers
– The paging unit is controlled by the contents of the
microprocessor’s control registers. See Figure 10 for the contents
of control registers CR0 through CR4. Note that these registers are
available to the 80386 through the Core2 microprocessors.
– Beginning with the Pentium, an additional control register labeled
CR4 controls extensions to the basic architecture provided in the
Pentium or newer microprocessor.
– The registers important to the paging unit are CR0 and CR3. The
leftmost bit (PG) position of CR0 selects paging when placed at a
logic 1 level. If the PG bit is cleared (0), the linear address
generated by the program becomes the physical address used to
access memory.
– If the PG bit is set (1), the linear address is converted to a physical
address through the paging mechanism. The paging mechanism
functions in both the real and protected modes.
2.4) MEMORY PAGING…

Paging Registers
– CR3 contains the page directory base or root address, and the PCD
and PWT bits.
– The PCD and PWT bits control the operation of the PCD and PWT
pins on the microprocessor.
– If PCD is set (1), the PCD pin becomes a logic one during bus
cycles that are not paged. This allows the external hardware to
control the level 2 cache memory. (Note that the level 2 cache
memory is an internal [on modern versions of the Pentium] high-
speed memory that functions as a buffer between the
microprocessor and the main DRAM memory system.)
Where ;
• PCD is the page cache disable output reflects the state of the PCD attribute
bit in the page table entry or the page directory entry and
• PWT is the page write through output indicates the state of the PWT
attribute bit in the page table entry or the page directory entry.
2.4) MEMORY PAGING…

Paging Registers

FIGURE 10 The control register structure of the microprocessor..


2.4 MEMORY PAGING…

Paging Registers
– The linear address, as it is generated by the software, is broken
into three sections that are used to access the

 page directory entry,


 page table entry, and
 memory page offset address.
– Figure 11 shows the linear address and its makeup for paging.

FIGURE 11 The format for the linear address (a)


and a page directory or page table entry (b).
2.4) MEMORY PAGING…

The Page Directory and Page Table


– The linear address, as it is generated by the software, is broken
into three sections that are used to access the

 page directory entry,


 page table entry, and
 memory page offset address.
– Figure 11 shows the linear address and its makeup for paging.

FIGURE 11 The format for the linear address (a)


and a page directory or page table entry (b).
Questions ?

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