Samara University College of Engineering and Technology Computer Science
Samara University College of Engineering and Technology Computer Science
Chapter 2
The Microprocessor and its Architecture
Outline
1. Describe the function and purpose of each program-visible register in the 8086–
Core2 microprocessors, including the 64-bit extensions.
2. Detail the flag register and the purpose of each flag bit.
3. Describe how memory is accessed using real mode memory-addressing techniques.
4. Describe how memory is accessed using protected mode memory-addressing
techniques.
5. Describe how memory is accessed using the 64-bit flat memory model.
6. Describe the program-invisible registers found within the 80286 through Core2
microprocessors.
7. Detail the operation of the memory-paging mechanism.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE
– Note : See topic 2.2 and 2.3 about real mode and
protected mode respectively
FIGURE 1 The programming
model of the 8086 through the
Core2 microprocessor including
the 64-bit extensions.
Multipurpose Registers
RAX – RAX is referenced as a 64-bit register (RAX), a 32-bit
(accumulator) register (EAX), a 16-bit register (AX), or as either of two 8-
bit registers (AH and AL). Note that if an 8- or 16-bit
register is addressed, only that portion of the 32-bit register
changes without affecting the remaining bits.
– The accumulator is used for instructions such as
multiplication, division, and some of the adjustment
instructions.
Multipurpose Registers
RCX – RCX, which is addressable as RCX, ECX, CX, CH, or CL,
(count) is a general-purpose register that also holds the count for
various instructions
– Instructions that use a count are the repeated string
instructions (REP/REPE/REPNE); and shift, rotate, and
LOOP/LOOPD instructions.
Multipurpose Registers
RBP – RBP, which is addressable as RBP, EBP, or BP, points to a
(Base pointer) memory location in all versions of the microprocessor for
memory data transfers
Multipurpose Registers
R8 through – These registers are only found in the Pentium 4 and Core2 if
R15 64-bit extensions are enabled. As mentioned, data in these
registers are addressed as 64-, 32-, 16-, or 8-bit sizes and are
of general purpose.
– Most applications will not use these registers until 64-bit
processors are common.
– Please note that the 8-bit portion is the rightmost 8-bit only;
bits 8 to 15 are not directly addressable as a byte.
Special-Purpose Registers
– The special-purpose registers include RIP, RSP, and
RFLAGS; and the segment registers include CS, DS, ES,
SS, FS, and GS.
Special-Purpose Registers
FLAGS – RFLAGS are special purpose registers which indicate the
condition of the microprocessor and control its operation.
Special-Purpose Registers
A (auxiliary – The auxiliary carry holds the carry (half-carry) after addition
carry) or the borrow after subtraction between bit positions 3 and 4
of the result..
Z (zero)) – The zero flag shows that the result of an arithmetic or logic
operation is zero. If Z=1 , the result is zero; if Z=0 , the
result is not zero. This may be confusing, but that is how
Intel decided to name this flag.
– The sign flag holds the arithmetic sign of the result after an
S (sign) arithmetic or logic instruction executes. If S=1 , the sign bit
(leftmost bit of a number) is set or negative; if S=0, the sign
bit is cleared or positive.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…
Special-Purpose Registers
T (trap) – The trap flag enables trapping through an on-chip debugging
feature. (A program is debugged to find an error or bug.) If
the T flag is enabled (1), the microprocessor interrupts the
flow of the program on conditions as indicated by the debug
registers and control registers. If the T flag is a logic 0, the
trapping (debugging) feature is disabled.
I (interrupt) – The interrupt flag controls the operation of the INTR
(interrupt request) input pin. If I=1, the INTR pin is enabled;
if I=0 , the INTR pin is disabled. The state of the I flag bit is
controlled by the STI (set I flag) and CLI (clear I flag)
instructions.
D (direction) – The direction flag selects either the increment or decrement
mode for the DI and/or SI registers during string
instructions. If , the registers are automatically decremented;
if , the registers are automatically incremented. The D flag is
set with the STD (set direction) and cleared with the CLD
(clear direction) instructions.
2.1) INTERNAL MICROPROCESSOR ARCHITECTURE…
Special-Purpose Registers
O (overflow) – Overflows occur when signed numbers are added or
subtracted. An overflow indicates that the result has
exceeded the capacity of the machine. For example, if 7FH
(+127 ) is added—using an 8-bit addition—to 01H (+1 ), the
result is 80H (–128). This result represents an overflow
condition indicated by the overflow flag for signed addition.
For unsigned operations, the overflow flag is ignored.
Special-Purpose Registers
NT (nested task) – The nested task flag indicates that the current task is nested
within another task in protected mode operation. This flag is
set when the task is nested by software.
Special-Purpose Registers
VIF (virtual – The VIF is a copy of the interrupt flag bit available to the
Pentium Pentium 4 microprocessors.
interrupt)
VIP (Virtual – VIP provides information about a virtual mode interrupt for
the Pentium up to Pentium 4 microprocessors. This is used
interrupt
in multitasking environments to provide the operating
pending) system with virtual interrupt flags and interrupt pending
information
Special-Purpose Registers
Segment – Additional registers, called segment registers, generate
memory addresses when combined with other registers in
Registers the microprocessor. There are either four or six segment
registers in various versions of the microprocessor.
CS (code) – The code segment is a section of memory that holds the code
(programs and procedures) used by the microprocessor. The
code segment register defines the starting address of the
section of memory holding code.
Special-Purpose Registers
ES (extra) – The extra segment is an additional data segment that is used
by some of the string instructions to hold destination data.
SS (stack) – The stack segment defines the area of memory used for the
stack.
– The stack entry point is determined by the stack segment and
stack pointer registers. The BP register also addresses data
within the stack segment.
– The 80286 and above operate in either the real or protected mode.
Only the 8086 and 8088 operate exclusively in the real mode. In
the 64-bit operation mode of the Pentium 4 and Core2, there is no
real mode operation.
– This section of the text details the operation of the microprocessor
in the real mode.
– Real mode operation allows the microprocessor to address only the
first 1M byte of memory space—even if it is the Pentium 4 or
Core2 microprocessor. Note that the first 1M byte of memory is
called the real memory, conventional memory, or DOS memory
system.
2.2) REAL MODE MEMORY ADDRESSING…
Program-Invisible Registers
– The global and local descriptor tables are found in the memory
system. In order to access and specify the address of these tables,
the 80286–Core2 contain program-invisible registers.
– The program-invisible registers are not directly addressed by
software so they are given this name (although some of these
registers are accessed by the system software).
– Figure 9 illustrates the program-invisible registers as they appear
in the 80286 through the Core2.
– These registers control the microprocessor when operated in
protected mode.
2.3) INTRODUCTION TO PROTECTED MODE
MEMORY ADDRESSING…
Program-Invisible Registers
Paging Registers
– The paging unit is controlled by the contents of the
microprocessor’s control registers. See Figure 10 for the contents
of control registers CR0 through CR4. Note that these registers are
available to the 80386 through the Core2 microprocessors.
– Beginning with the Pentium, an additional control register labeled
CR4 controls extensions to the basic architecture provided in the
Pentium or newer microprocessor.
– The registers important to the paging unit are CR0 and CR3. The
leftmost bit (PG) position of CR0 selects paging when placed at a
logic 1 level. If the PG bit is cleared (0), the linear address
generated by the program becomes the physical address used to
access memory.
– If the PG bit is set (1), the linear address is converted to a physical
address through the paging mechanism. The paging mechanism
functions in both the real and protected modes.
2.4) MEMORY PAGING…
Paging Registers
– CR3 contains the page directory base or root address, and the PCD
and PWT bits.
– The PCD and PWT bits control the operation of the PCD and PWT
pins on the microprocessor.
– If PCD is set (1), the PCD pin becomes a logic one during bus
cycles that are not paged. This allows the external hardware to
control the level 2 cache memory. (Note that the level 2 cache
memory is an internal [on modern versions of the Pentium] high-
speed memory that functions as a buffer between the
microprocessor and the main DRAM memory system.)
Where ;
• PCD is the page cache disable output reflects the state of the PCD attribute
bit in the page table entry or the page directory entry and
• PWT is the page write through output indicates the state of the PWT
attribute bit in the page table entry or the page directory entry.
2.4) MEMORY PAGING…
Paging Registers
Paging Registers
– The linear address, as it is generated by the software, is broken
into three sections that are used to access the