(Autonomous IARE UG-20)

MICROPROCESSORS AND MICROCONTROLLERS

Topic: ARM instruction set – Data processing Instructions

Dr. D Khalandar Basha

Associate Professor
ELECTRONICS AND COMMUNICATION ENGINEERING Don’t write or place any
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INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
DUNDIGAL, HYDERABAD - 500 043
Dr. D Khalandar Basha

ARM instruction set

Data processing Instructions

The slides are prepared by referring

“ARM System Developer’s Guide Designing and Optimizing
System Software ”

Authors:
Andrew N. Sloss Dominic Symes Chris Wright
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Publication: image in this area

Morgan Kaufmann PublishersS

Dr. D Khalandar Basha

Data processing Instructions

The data processing instructions manipulate data within registers.

They are move instructions, arithmetic instructions, logical instructions,
comparison instructions, and multiply instructions.
Most data processing instructions can process one of their operands using the
barrel shifter.
If the S suffix is used on a data processing instruction, then it
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updates the flags in the CPSR. image in this area
These instructions only work on registers, NOT memory.
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Data processing Instructions

Data processing instructions consist of :

Data movement: MOV MVN
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Multiplication: MUL MLA
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Syntax: <Operation> {<cond>} {S} Rd, Rn, Operand2 image in this area
Second operand is sent to the ALU via barrel shifter.
Data movement does not specify Rn
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Data processing Instructions [1]

Data processing instructions are processed within the
ALU.
One operand passed through Rn register and the
second operand with or without barrel shifter.
 A unique and powerful feature of the ARM processor is
the ability to shift the 32- bit binary
pattern in one of the source registers
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left or right by a specific number of image in this area
positions before it enters the ALU
Fig. 1: Barrel shifter and ALU through barrel shifter.
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Data processing Instructions [1]

N shift operations Syntax
Table 1 gives
Immediate #immediate
Register Rm Barrel shift
Logical shift left by immediate Rm, LSL #shift_imm operation syntax for
Logical shift left by register Rm, LSL Rs data processing inst
Logical shift right by immediate Rm, LSR #shift_imm
Logical shift right with register Rm, LSR Rs
Arithmetic shift right by immediate Rm, ASR #shift_imm
Arithmetic shift right by register Rm, ASR Rs Don’t write or place any
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Rotate right by immediate Rm, ROR #shift_imm
Rotate right by register Rm, ROR Rs
Rotate right with extend Rm, RRX
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Data processing Instructions

There are few data processing instructions that do not use the
barrel shift, for example, the MUL (multiply), CLZ (count leading zeros),
and QADD (signed saturated 32-bit add) instructions.

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Dr. D Khalandar Basha

Data processing Instructions

Data movement
These instructions copy the data N into the register.
The various instructions are
MOV, MVN
Syntax: <Operation> {<cond>} {S} Rd, N

MOV Move a 32-bit value into a register Rd = N Don’t write or place any
MVN move the NOT of the 32-bit value Rd = ∼N image in this area
into a register
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Data movement Instructions – MOV, MVN

MOV - Move a 32-bit value into a register

Syntax: MOV Rd, N
This instruction move a value N to the register Rn.
 Rd<= N

MVN – Move the NOT of the 32-bit value into a register

Syntax: MVN Rd, N
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This instruction move the complimented value of N to register Rn. image in this area

 Rd<= ~N
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Data movement Instructions – MOV, MVN

 MOV r7, r5 r7 <= r5

 MOV r7, r5, LSL #2 r7 <= r5 after shifting r5 by 2 bits

 MOV r0, r1, LSL #1 r0 <= r1 after shifting r1 by 1 bit

Flags will be updated
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Dr. D Khalandar Basha

Data processing Instructions

Arithmetic Instructions
The arithmetic instructions implement addition and subtraction of 32-bit signed
and unsigned values.
The various instructions are
ADD, ADC, RSB, RSC, SUB, SBC

Syntax: <instruction> {<cond>} {S} Rd, Rn, N Don’t write or place any
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Arithmetic Instructions - ADD

ADD - add two 32-bit values.

Syntax: ADD Rd, Rn, N
This instruction add a value stored in register Rn with N. The result is stored in
register Rd.
 Rd <= Rn + N

Syntax: ADDS Rd, Rn, N

This instruction add a value stored in register Rn with N. Don’t write or place any
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The result is stored in Rd and the CPSR is updated with the flags.
 Rd <= Rn + N
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Arithmetic Instructions - ADC

ADC - add two 32-bit values along with carry.

Syntax: ADC Rd, Rn, N
This instruction add a value stored in register Rn with N along with the carry flag.

The result is stored in register Rd.

 Rd <= Rn + N + CY

Syntax: ADCS Rd, Rn, N Don’t write or place any

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This instruction add a value stored in reg Rn with N along with
the carry. The result is stored in reg Rd and the CPSR is updated with the flags
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Arithmetic Instructions - RSB

RSB - reverse subtract of two 32-bit values.

Syntax: RSB Rd, Rn, N
This instruction (RSB) subtracts Rn from N, writing the result to Rd. This
instruction can use to negate numbers.
 Rd <= N - Rn

Syntax: RSBS Rd, Rn, N

This instruction (RSB) subtracts Rn from N, writing the result Don’t write or place any
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to Rd and the CPSR is updated with the flags
 Rd <= N - Rn
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Arithmetic Instructions - RSC

RSC - reverse subtract with carry of two 32-bit values.

Syntax: RSC Rd, Rn, N
This instruction (RSC) subtracts Rn from N along carry flag, writing the result to
Rd. This instruction can use to negate numbers.
 Rd <= N - Rn - ! (Carry flag)

Syntax: RSCS Rd, Rn, N

This instruction (RSC) subtracts Rn from N along carry flag, writing Don’t write or place any
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the result to Rd and the CPSR is updated with the flags
 Rd <= N - Rn - ! (Carry flag)
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Arithmetic Instructions - SUB

SUB – subtract two 32-bit values.

Syntax: SUB Rd, Rn, N
This instruction (SUB) subtracts N from Rn, writing the result to Rd.
 Rd <= Rn – N

Syntax: SUBS Rd, Rn, N

This instruction (SUBS) subtracts N from Rn, writing the result to
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Rd and the CPSR is updated with the flags image in this area
 Rd <= Rn - N
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Arithmetic Instructions - SBC

SBC – subtract with carry of two 32-bit values.

Syntax: SBC Rd, Rn, N
This instruction (SBC) subtract N from Rn along with carry flag, writing the result
to Rd.
 Rd <= Rn – N - ! (Carry flag)

Syntax: SBCS Rd, Rn, N

This instruction (SBCS) subtracts N from Rn along with carry flag, Don’t write or place any
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writing the result to Rd and the CPSR is updated with the flags
 Rd <= Rn – N - ! (Carry flag)
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Arithmetic Instructions - Summary

ADD ADC add two 32-bit values Rd = Rn + N

ADC ADC add two 32-bit values and carry Rd = Rn + N+ CY
RSB Reverse subtract of two 32-bit values Rd = N − Rn
RSC Reverse subtract with carry of two Rd = N − Rn − !
32-bit values (carry flag)
SUB Subtract two 32-bit values Rd = Rn − N
SBC Subtract with carry of two 32-bit Rd = Rn − N− !
values (carry flag)
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Arithmetic Instructions

Example
 SUB r0, r1, r2

PRE POST

r0 = 0x00000000 r0 = 0x00000001
r1 = 0x00000002
r2 = 0x00000001
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Dr. D Khalandar Basha

Arithmetic Instructions

Example
 SUBS r1, r1, #1;

PRE POST

cpsr = nzcvqiFt_USER cpsr = nZcvqiFt_USER

r1 = 0x00000001 r1 = 0x00000000

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Dr. D Khalandar Basha

Arithmetic Instructions

Example
 RSB r0, r1, #0 ; Rd = 0x0 - r1

PRE POST

r0 = 0x00000000 r0 = -r1 = 0xffffff89

r1 = 0x00000077

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Dr. D Khalandar Basha

Arithmetic Instructions

Example
 RSB r0, r1, #0 ; Rd = 0x0 - r1

PRE POST

r0 = 0x00000000 r0 = -r1 = 0xffffff89

r1 = 0x00000077

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Dr. D Khalandar Basha

Barrel Shifter with Arithmetic Instructions

 The wide range of second operand shifts available on arithmetic and logical
instructions is a very powerful feature of the ARM instruction set.
ADD r0, r1, r1, LSL #1

PRE POST

r0 = 0x00000000 r0 = 0x0000000f
r1 = 0x00000005 r1 = 0x00000005
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Register r1 is first shifted one location to the left to give the value of twice r1. image in this area
The ADD instruction then adds the result of the barrel shift operation to
register r1.
The final result in register r0 is equal to three times the value in register r1.
Dr. D Khalandar Basha

Data processing Instructions

Logical Instructions
Logical instructions perform bitwise logical operations on the two source registers.
The various instructions are
AND, ORR, EOR, BIC

Syntax: <instruction> {<cond>} {S} Rd, Rn, N

The logical instructions update the cpsr flags only if the S suffix Don’t write or place any
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is present. These instructions can use barrel-shifted second
operands in the same way as the arithmetic instructions.
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Logical Instructions - AND

AND - logical bitwise AND of two 32-bit values.

Syntax: AND Rd, Rn, N
This instruction AND bit by bit between the value stored in register Rn with N.
The result is stored in register Rd.
 Rd<= Rn & N
Syntax: ANDS Rd, Rn, N
This instruction AND bit by bit between the value stored in register
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Rn with N. The result is stored in Rd and the CPSR is updated with image in this area

the flags
 Rd<= Rn & N
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Logical Instructions - ORR

ORR- logical bitwise OR of two 32-bit values.

Syntax: ORR Rd, Rn, N
This instruction OR bit by bit between the value stored in register Rn with N. The
result is stored in register Rd.
 Rd <= Rn | N
Syntax: ORRS Rd, Rn, N
This instruction OR bit by bit between the value stored in register
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Rn with N. The result is stored in Rd and the CPSR is updated
with the flags
 Rd<= Rn | N
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Logical Instructions - EOR

EOR- logical bitwise EX-OR of two 32-bit values.

Syntax: EOR Rd, Rn, N
This instruction EX-OR bit by bit between the value stored in register Rn with N.
The result is stored in register Rd.
 Rd <= Rn ^ N (^ is logical EX-OR)
Syntax: EORS Rd, Rn, N
This instruction EX-OR bit by bit between the value stored in register
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Rn with N. The result is stored in Rd and the CPSR is updated image in this area

with the flags

 Rd<= Rn ^ N
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Logical Instructions - BIC

BIC- logical clear (AND NOT). This instruction is particularly useful when clearing
status bits and is frequently used to change interrupt masks in the cpsr.
Syntax: BIC Rd, Rn, N
This instruction logic bit clear bit by bit between the value stored in register Rn
with N. The result is stored in register Rd.
 Rd<= Rn & ~N
Syntax: BICS Rd, Rn, N Don’t write or place any
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This instruction logic bit clear bit by bit between the value stored
In Rn with N. The result is stored in Rd and the CPSR is updated
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Logical Instructions

Example
 ORR r0, r1, r2

PRE POST

r0 = 0x00000000 r0 = 0x12345678
r1 = 0x02040608
r2 = 0x10305070
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Dr. D Khalandar Basha

Logical Instructions

Example
 BIC r0, r1, r2

PRE POST

r1 = 0b1111 0b1010
r2 = 0b0101

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This is equivalent to Rd = Rn AND NOT(N)
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Data processing Instructions

Comparison Instructions
The comparison instructions are used to compare or test a register with a 32-bit
value.
They update the CPSR flag bits according to the result, but do not affect other
registers.
The various instructions are
 CMP, CMN, TEA, TST Don’t write or place any
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Syntax: <instruction> {<cond>} Rn, N
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Comparison Instructions - CMP

CMP- comparison of two 32-bit values.

Syntax: CMP Rn, N

The CMP is effectively a subtract instruction with the result discarded. The result
affects the flags in CPSR.
 Flags <= Rn – N
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Comparison Instructions - CMN

CMN- compare negated of two 32-bit values.

Syntax: CMN Rn, N

The CMN is effectively a add instruction with the result discarded. The result
affects the flags in CPSR.
 Flags <= Rn + N
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Comparison Instructions – TEQ

TEQ - test for equality of two 32-bit values.

Syntax: TEQ Rn, N

The TEQ is a logical exclusive OR operation. For each, the results are discarded
but the condition bits are updated in the CPSR.
 Flags <= Rn ^ N
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Comparison Instructions - TST

TST - test bits of two 32-bit values.

Syntax: TST Rn, N

The TST is a logical AND operation. For each, the results are discarded but the
condition bits are updated in the CPSR.
 Flags <= Rn & N
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Logical Instructions

Example
 CMP r0, r9

PRE POST

cpsr = nzcvqiFt_USER cpsr = nZcvqiFt_USER

r0 = 4 r0 = 4
r9 = 4 r9 = 4
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This is equivalent to Rd = Rn AND NOT(N)
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Data processing Instructions

Multiply Instructions
The multiply instructions multiply the contents of a pair of registers and, depending
upon the instruction, accumulate the results in with another register.
The long multiplies accumulate onto a pair of registers representing
a 64-bit value. The final result is placed in a destination register or
a pair of registers.
The various instructions are Don’t write or place any
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 MUL, MLA
 SMULL, UMULL, SMLAL, UMLAL
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Multiply Instructions - MUL

MUL – multiply two 32-bit values. Product is 32 bits

Syntax: MUL {<cond>} {S} Rd, Rm, Rs

The MUL instruction, multiply the contents of Rm and Rs registers and the results

store in Rd register.
 Rd <= Rm * Rs Don’t write or place any
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 If S suffix is added then the result affects the flags in CPSR.

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Multiply Instructions - MLA

MLA – multiply and accumulate two 32-bit values.

Syntax: MLA {<cond>} {S} Rd, Rm, Rs, Rn

The MLA instruction, multiply the contents of Rm and Rs registers and

accumulate with Rn register, the result stored in Rd register.
 Rd <= (Rm * Rs) + Rn
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 If S suffix is added then the result affects the flags in CPSR.
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Data processing Instructions

Long Multiply Instructions

The long multiplies accumulate onto a pair of registers representing a 64-bit value.
The final result is placed in a destination register or a pair of registers.
Syntax: <instruct ion> {<cond>} RdLo, RdHi, Rm, Rs
The various instructions are
 SMULL, UMULL, SMLAL, UMLAL
The long multiply instructions produce a 64-bit result.
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The result is too large to fit a single 32-bit register so the result image in this area

is placed in two registers RdLo and RdHi. RdLo holds the lower
32 bits, and RdHi holds the higher 32 bits of the 64-bit result.
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Long Multiply Instructions - SMULL

SMULL – signed multiply long two 32-bit values, the result is 64 bits.
Syntax: SMULL {<cond>} {S} RdLo, RdHi, Rm, Rs

The SMULL instruction, is signed multiplication of Rm and Rs registers

contents and register RdLo contains the lower 32 bits, and
register RdHi contains the higher 32 bits of the 64-bit result.
 [RdHi, RdLo] <= Rm * Rs Don’t write or place any
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 If S suffix is added then the result affects the flags in CPSR.

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Long Multiply Instructions - UMULL

UMULL – Unsigned multiply long two 32-bit values, the result is 64 bits.
Syntax: UMULL {<cond>} {S} RdLo, RdHi, Rm, Rs

The UMULL instruction, is unsigned multiplication of Rm and Rs registers

contents and register RdLo contains the lower 32 bits, and
register RdHi contains the higher 32 bits of the 64-bit result.
 [RdHi, RdLo] <= Rm * Rs Don’t write or place any
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 If S suffix is added then the result affects the flags in CPSR.

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Long Multiply Instructions - SMULL

SMLAL – Unsigned multiply accumulate long two 32-bit values, the result is 64 bits.
Syntax: SMLAL {<cond>} {S} RdLo, RdHi, Rm, Rs
The SMLAL instruction, is signed multiplication of Rm and Rs registers and
accumulate the product to [RdHi, RdLo] contents and
register RdLo contains the lower 32 bits, and
register RdHi contains the higher 32 bits of the 64-bit result.
. [RdHi, RdLo] <= [RdHi, RdLo] + Rm * Rs Don’t write or place any
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 If S suffix is added then the result affects the flags in CPSR.

Dr. D Khalandar Basha

Long Multiply Instructions - UMLAL

UMLAL – Unsigned multiply accumulate long two 32-bit values, the result is 64 bits.
Syntax: UMLAL {<cond>} {S} RdLo, RdHi, Rm, Rs

The UMLAL instruction, is unsigned multiplication of Rm and Rs registers and

accumulate the product to [RdHi, RdLo] contents and
register RdLo contains the lower 32 bits, and
register RdHi contains the higher 32 bits of the 64-bit result. Don’t write or place any
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 [RdHi, RdLo] <= [RdHi, RdLo] + Rm * Rs
Dr. D Khalandar Basha

MICROPROCESSORS AND MICROCONTROLLERS

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