Unit-II

Input/output Organization
Accessing Input/output devices
Input/output (I/O) refers to the communication between a computer and
the outside world. Input/output devices connect peripheral devices to the
CPU.
The block diagram of an Input-Output Interface unit contain the following
blocks :

1. Data Bus Buffer

2. Read/Write Control Logic
3. Port A, Port B register
4. Control and Status register
Data Bus Buffer :
• The bus buffer use bi-directional data bus to communicate with CPU.
• All control word data and status information between interface unit and CPU are transferred
through data bus.
Port A and Port B :
• Port A and Port B are used to transfer data between Input-Output device and Interface Unit.
• Each port consist of bi-directional data input buffer and bi-directional data output buffer.
• Interface unit connect directly with an input device and output disk or with device that
require both input and output through Port A and Port B i.e. modem, external hard-drive,
magnetic disk.
Control and Status Register :
• CPU gives control information to control register on basis of control information.
• Interface unit control input and output operation between CPU and input-output device.
• Bits which are present in status register are used for checking of status conditions.
• Status register indicate status of data register, port A, port B and also record error that may
be occur during transfer of data.
Read/Write Control Logic :
• This block generates necessary control signals for overall device operations.
• All commands from CPU are accepted through this block.
• It also allow status of interface unit to be transferred onto data bus through
this block accept CS, read and write control signal from system bus and S 0 ,
S1 from system address bus.
• Read and Write signal are used to define direction of data transfer over data
bus.
• The read signal direct data transfer from interface unit to CPU and write signal direct data
transfer from CPU to interface unit through data bus.
• Address bus is used to select to interface unit.
• Two least significant lines of address bus ( A0 , A1 ) are connected to select lines S0, S1.
• This two select input lines are used to select any one of four registers in interface unit.
• The selection of interface unit is according to the following criteria :
Read state :
Chip Select Operation Select lines
Selection of
Interface unit
CS Read Write S0 S1

0 0 1 0 0 Port A

0 0 1 0 1 Port B

0 0 1 1 0 Control Register

0 0 1 1 1 Status Register
 Write State :

Chip Select Operation Select lines

Selection of
Interface unit
CS Read Write S0 S1

0 1 0 0 0 Port A

0 1 0 0 1 Port B

0 1 0 1 0 Control Register

0 1 0 1 1 Status Register

Example :
•If S0, S1 = 0 1, then Port B data register is selected for data transfer between CPU and I/O
device.
•If S0, S1 = 1 0, then Control register is selected and store the control information send by the
CPU.
 Interrupts
An interrupt is a signal emitted by a device attached to a computer or from a
program within the computer. It requires the operating system (OS) to stop and
figure out what to do next.

Interrupt Hardware:
A hardware interrupt is an electronic signal from an external hardware device
that indicates it needs attention from the OS.

One example of this is moving a mouse or pressing a keyboard key. In these

examples of interrupts, the processor must stop to read the mouse position or
keystroke at that instant.
 Enabling and Disabling Interrupts
Enabling and disabling interrupts is a crucial aspect of computer organization, especially in
systems that handle multiple tasks concurrently.
Enabling Interrupts:
• When interrupts are enabled, the processor is configured to respond to interrupt signals.
• This means that when an interrupt request occurs, the processor will temporarily suspend its
current task, save its state, and jump to an interrupt service routine (ISR) to handle the
interrupt.
• Enabling interrupts allows for efficient multitasking and responsiveness in a system.

Disabling Interrupts:
• Conversely, disabling interrupts prevents the processor from responding to interrupt signals.
• When interrupts are disabled, the processor ignores any incoming interrupt requests.
• This can be useful in critical sections of code where interrupt handling could cause
undesirable behavior or when the system needs to perform tasks that require uninterrupted
execution.
 Handling Multiple Devices
Handling multiple devices in computer organization involves managing the
interactions between the central processing unit (CPU) and various peripheral
devices connected to the system.

Input/Output (I/O) Operations:

• Devices such as keyboards, mice, monitors, disk drives, network interfaces, etc.,
communicate with the CPU through I/O operations.
• These operations involve transferring data between the CPU and the device.
Device Controllers:
• Each peripheral device is controlled by a device controller, which is responsible
for managing the device's operations and interfacing with the CPU.
• Device controllers typically have registers and control logic to manage data
transfers and device-specific functionalities.
Interrupts:
• When a peripheral device needs attention from the CPU (e.g., data is ready to be
read, a task is completed, an error occurs), it generates an interrupt signal.
• The CPU interrupts its current execution to handle the request from the device.
• Interrupt handling involves saving the CPU's current state, servicing the
interrupt (handling the request), and then restoring the CPU's state to continue its
previous task.
Interrupt Prioritization:
• In systems with multiple devices, it's essential to prioritize interrupts to ensure
that critical tasks are handled promptly.
• Interrupt controllers are used to prioritize interrupts based on their importance or
urgency.
• They may also handle interrupt masking, where certain interrupts are
temporarily disabled to prevent them from interrupting higher-priority tasks.
Polling vs. Interrupts:
• There are two primary methods for handling communication between the CPU and devices: polling
and interrupts.
• Polling involves the CPU continuously checking the status of devices to determine if they need
attention.
• Interrupts allow devices to signal the CPU only when necessary, reducing CPU overhead and
improving system responsiveness.
Direct Memory Access (DMA):
• For high-speed data transfers between devices and memory without involving the CPU, DMA
controllers are used.
• DMA allows devices to access system memory directly, bypassing the CPU for data transfers.
• This is particularly useful for devices that transfer large amounts of data, such as disk drives or
network interfaces.
Device Drivers:
• Device drivers are software components that facilitate communication between the operating
system and peripheral devices.
• They abstract the device's hardware details, providing a standardized interface for the operating
system to interact with different types of devices.
 Direct Memory Access

DMA (Direct memory access) is the special feature within the computer system that
transfers the data between memory and peripheral devices(like hard drives) without
the intervention of the CPU.

This improves system performance by off loading data transfer tasks from the CPU,
allowing it to focus on other processing tasks.
Modes of Data Transfer in DMA
There are 3 modes of data transfer in DMA that are described below.

• Burst Mode: In Burst Mode, buses are handed over to the CPU by the
DMA if the whole data is completely transferred, not before that.
• Cycle Stealing Mode: In Cycle Stealing Mode, buses are handed over
to the CPU by the DMA after the transfer of each byte. Continuous
request for bus control is generated by this Data Transfer Mode. It
works more easily for higher-priority tasks.
• Transparent Mode: Transparent Mode in DMA does not require any
bus in the transfer of the data as it works when the CPU is executing
the transaction.
• The above block diagram of the DMA controller.
• The unit communicates with the CPU through the data bus and control lines.
• Through the use of the address bus and allowing the DMA and RS register to
select inputs, the register within the DMA is chosen by the CPU.
• RD and WR are two-way inputs.
• When BG (bus grant) input is 0, the CPU can communicate with DMA
registers.
• When BG (bus grant) input is 1, the CPU has relinquished the buses and
DMA can communicate directly with the memory.
• The CPU initializes the DMA by sending the given information through
the data bus.

• The starting address of the memory block where the data is available (to read)
or where data are to be stored (to write).

• It also sends word count which is the number of words in the memory block to
be read or written.

• Control to define the mode of transfer such as read or write.

• A control to begin the DMA transfer

Advantages of DMA:
• Speed: The data transfers are faster than the CPU-managed data
transfers because it doesn’t require CPU involvement in each byte.

• Efficiency: Its reduces the CPU overhead, by allowing it to focus on

other tasks.

• Parallelism: Multiple DMA channels works simultaneously which

improves the system performance in terms of throughput.

• Reduced Latency: System can become more responsive by DMA

transfers because it allows CPU to focus on other tasks.
 Disadvantages of DMA:
• Compatibility Issues: DMA configurations may not always be compatible
across different hardware systems.

• Complexity: The complexity increase as we are writing the DMA command

block into the memory which contain all the sources and destinations of data
transfer that are not contiguous.

• Limited Control: As DMA takes control over the memory bus for data
transfers which is not always acceptable because in some situations CPU has to
wait for the DMA controller to complete the task.

• Resource Conflicts: In some of DMA capable devices there can be memory

conflict when multiple devices attempts to use DMA simultaneously.
Buses- Synchronous and Asynchronous.
A synchronous bus uses a clock signal to synchronize the timing of the
sender and receiver.
An asynchronous bus does not require a common clock signal.
Synchronous buses:
• A synchronous bus is a type of bus in which all the devices connected
to the bus are synchronized with each other.
• In a synchronous bus, the data transfer is done in a clock-driven
manner.
• The bus is controlled by a master device, and all the slave devices
connected to the bus are synchronized with the clock signal generated
by the master.
• The clock signal is used to synchronize the transfer of data between
the devices connected to the bus.
Synchronous Bus Timing Diagram
Synchronous Bus
Asynchronous buses:
• An asynchronous bus is a type of bus in which the devices connected to the bus
are not synchronized with each other.
• In an asynchronous bus, the data transfer is done without any clock signal.
Instead, each device has its own timing mechanism, and the data transfer is
initiated by the device when it is ready to transfer data.
• The bus is not controlled by any master device, and the devices connected to the
bus communicate with each other independently.
The main advantage of a synchronous bus is that it provides higher data
transfer rates and greater efficiency, as all the devices are synchronized with
each other.
However, synchronous buses are more complex and expensive to implement than
asynchronous buses.
Asynchronous buses are simpler and cheaper to implement, but they offer lower
data transfer rates and are less efficient than synchronous buses.
Asynchronous Bus