COE 372 Sem2, 2022/23

SRAM Cells
 Lecture Overview
• Memory Basics
• SRAM Basics
• Multiport SRAM
• SRAM Arrays
• SRAM Block Architecture
• SRAM Array Addressing

• Conclusion
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 Memory Basics
• RAM: Random Access Memory
– historically defined as memory array with individual bit access
– refers to memory with both Read and Write capabilities
• ROM: Read Only Memory
– no capabilities for “online”memory Write operations
– Write typically requires high voltages or erasing by UV light
• Volatility of Memory
– volatile memory loses data over time or when power is removed
• RAM is volatile
– non-volatile memory stores date even when power is removed
• ROM is non-volatile
• Static vs. Dynamic Memory
– Static: holds data as long as power is applied (SRAM)
– Dynamic: must be refreshed periodically (DRAM)
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 SRAM Basics (1)
• SRAM = Static Random Access Memory
– Static: holds data as long as power is applied
– Volatile: can not hold data if power is removed
• 3 Operation States
– hold
– write
– read
• Basic 6T (6 transistor) SRAM Cell
– bistable (cross-coupled) INVs for storage
– access transistors MAL & MAR
• access to stored data for read and write
– word line, WL, controls access
• WL = 0, hold operation
• WL = 1, read or write operation
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 SRAM Basics (2)
• Hold
– word line = 0, access transistors are OFF
– data held in latch
• Write
– word line = 1, access tx are ON
– new data (voltage) applied to bit and bit_bar
– data in latch overwritten with new value
• Read
– word line = 1, access tx are ON
– bit and bit_bar read by a sense amplifier
• Sense Amplifier
– basically a simple differential amplifier
– comparing the difference between bit and bit_bar
• if bit > bit_bar, output is 1
• if bit < bit_bar, output is 0
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• allows output to be set quickly without fully charging/discharging bit line
 SRAM Basics (2)
• Cell size accounts for most of array size
– Reduce cell size at expense of complexity
• 6T SRAM Cell
– Used in most commercial chips
– Data stored in cross-coupled inverters
• Hold
– word line = 0, access transistors are OFF
– data held in latch

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 SRAM Basics (3)
• Write:
– Drive data onto bit, bit_b
– Raise wordline
• Read:
– Precharge bit, bit_b
– Raise wordline

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 SRAM Read
• Precharge both bitlines high
• Then turn on wordline
• One of the two bitlines will be pulled down by the cell
• Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
• Read stability
– A must not flip
– N1 >> N2

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 SRAM Write
• Drive one bitline high, the other low
• Then turn on wordline
• Bitlines overpower cell with new value
• Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
• Writability
– Must overpower feedback inverter
– N2 >> P1

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 Multi-Port SRAM (1)
• Allows multiple access to the same SRAM cell
simultaneously
– Provide high data bandwidth
• Applications
– Register file
– Cache
– Network switch
– ASIC etc.
• A multi-port SRAM cell schematic. Each port has
– two access transistors
– a pair of bitlines
– one word selection line
– one address decoder
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 Multi-Port SRAM (2)
• Challenges in multi-ports SRAM
– layout size increases quadratically with # of ports
• more word selection lines
• more pairs of bitlines
– lower speed and higher power consumption

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 SRAM Arrays
• N x n array of 1-bit cells
– n = word width; 8, 16, 32, etc.
– N = number of words
– m = number of address bits
• max N =
• Array I/O
– data, in and out
• Dn-1 downto D0
– address
• Am-1 downto A0
– control
• varies with design
• WE = write enable (assert low)
– WE=1=read, WE=0=write
• En = block enable (assert low)
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 SRAM Block Architecture
• Example: 2-Core design
– core width = k•n
• n = SRAM word size; 8, 16, etc.
• k = multiplier factor, 2,3,4,etc.
– shared word-line circuits
• horizontal word lines
• WL set by row decoder
– placed in center of 2 cores
– WL in both cores selected at same time

• Addressing Operation
– address word determines which row is
active (i.e. WL =1) via row decoder
– row decoder outputs feed row drivers
• buffers to drive large WL capacitance
• Physical Design
– layout scheme matches regular
patterning shown in schematic
• horizontal and vertical routing
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 SRAM Column Example

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 SRAM Array Addressing (1)
• Standard SRAM Addressing Scheme
– consider an Nx n SRAM array
• N = number of words, e.g., 512, 2k
• n = word size, e.g., 8 or 16
– m address bits are divided into r row bits and c column bits (r+c=m)
• addressable locations, N, is given by , r bits are decoded into x lines and c bits into y lines
• array organized with both vertical and horizontal stacks of words

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 Summary

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