Unit 4

Computer Organization

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 Computer Organization: Introduction: Function and structure
of a computer Functional components, Interconnection of
components,
Processing Unit: Organization of a processor - Registers, ALU
and Control unit, Data path in a CPU, Instruction cycle,
Input/Output Subsystem: Access of I/O devices, I/O ports, I/O
interfaces - Serial port, Parallel port, PCI bus, SCSI bus, USB
bus, I/O peripherals - Input devices, Output devices,
Secondary storage devices.
Memory Subsystem: Memory cells - SRAM and DRAM cells,
Internal Organization of a memory chip, Organization of a
memory unit.

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 Outline
 Functional Components
 Processing unit
 Input/Output subsystem
 Memory Subsystem

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 Functional Units
 A computer consists of three main parts:
 A processor (CPU)
 A main-memory system
 An I / O system
 The CPU consists of a control unit, registers, the
arithmetic and logic unit, the instruction execution unit,
and the interconnections among these components
 The information handled by a computer
 Instruction
 Govern the transfer information within a computer as well as
between the computer and its I / O devices
 Specify the arithmetic and logic operations to be performed
 Data
 Numbers and encoded characters that are used as operands by the
instructions
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 Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
 Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
 Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Login
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
 Main Memory System

Address Data/Instruction

Central Processing Unit (CPU)

Operational
Registers Arithmetic Instruction
and
Cache Logic Unit
Sets
memory Program

Counter

Control Unit

Input/Output System

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 Progra
 m performs a task is called a
A list of instructions that
program
 The program usually is stored in a memory called
program memory
 The computer is completely controlled by the
stored
program, except for possible external interruption by an
operator or by I / O devices connected to the machine
 Information handled by a computer must be encoded in a
suitable format. Most present-day hardware employs
digital circuits that have only two stable states, 0 (OFF)
and 1 (ON)

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 Memory Unit
 Memory
 The storage area in which programs are kept when they are
running and that contains the data needed by the running
programs
 Types of memory
 Volatile memory: storage that reta ins data only if it is receiving
power, such as dynamic random access memory (DRAM)
 Nonvolatile memory: a form of memory that retains data even in
the absence of a power source and that is used to store programs
between runs, such as flash memory
 Usually, a computer has two classes of storage
 Primary memory and secondary memory
 Primary memory
 Also called main memory. Volatile memory used to hold
programs while they are running; typically consists of DRAM in
today’s computers

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 Memory Unit
 Secondary memory
 Nonvolatile memory used to st ore programs and data between
runs; typically consists of magnetic disks in today’s
computers
 The memory consists of storage cells, each capable of
storing one bit of information
 The storage cells are processed in groups of fixed
size called words
 To provide easy access to any word in the memory, a distinct
address is associated with each word location
 The number of bits in each word is often referred to as the
word length of the computer
 Typical word length from 16 to 64 bits
 The capacity of the memory is one factor that
characterizes the size of a computer
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 Memory Unit
 Instruction and data can be written into the memory or
read out under the control of the processor
 It is essential to be able to access any word location in the
memory as quickly as possible
 Memory in which any location can be reached in a short and
fixed amount of time after spec ifying its address called random-
access memory (RAM)
 The time required to access one word is called the
memory access time
 This time is fixed, independent of the location of the word being
accessed
 The memory of a computer is normally implemented
as a memory hierarchy of three or four levels
 The small, fast, RAM units are called caches
 The largest and slowest unit is referred to as the main memory

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 Arithmetic and Logic Unit
 Most computer operations are performed in the
arithmetic and logic unit (ALU) of the processor
 For example, consider two numbers stored in the memory
are to be added
 They are brought into the processor, and the actual addition is
carried out by the ALU. Then su m may be stored in the memory
or retained in the processor for immediate use
 Typical arithmetic and logic operation
 Addition, subtraction, multiplic ation, division, comparison,
complement, etc.
 When operands are brought into the processor, they are
stored in high-speed storage elements called registers.
 Each register can store one word of data

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 Control Unit
 The control unit is the nerve center that sends control
signals to other units and senses their states
 Thus the control unit serves as a coordinator of the memory,
arithmetic and logic, and input / output units
 The operation of a computer can be summarized as
follows:
 The computer accepts information in the form of programs and
data through an input unit and stores it in the memory
 Information stored in the memo ry is fetched, under program
control, into an ALU, where it is processed
 Processed information leaves the computer through an output
unit
 All activities inside the machine are directed by the control
unit

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 Computer Components: Top-Level View

Memory Input/Output

System Bus

MAR MDR
Control
PC R0
Processor R1
IR .
.
. ALU
Rn-1
n general purpose registers

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 Interconnection Between Functional
Components
The functional components usually use a bus architecture for communication.
A bus is a collection of wires used for the communication of different parts of a computer.
Further, it uses electric signals to pass the data and information.

Bus Architecture

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 Different Types of Buses used are:
1. Address Bus
The address bus is used to communicate the address of the given data and
instructions.
2.Data Bus
The data bus is used to communicate the data from one part to another.
3.Bus
The control bus is used to control the signals between different
devices. Therefore, in conclusion, we can say that these functional components
communicate through this bus architecture. The input device takes the input, then
the data is processed and the output devices display the results. Besides, the
system bus performs all the communication that the cycle involves.

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 Bus Structures
 A group of lines that serves a connecting path for several
devices is called a bus
 In addition to the lines that carry the data, the bus must have
lines for address and control purposes
 The simplest way to interconnect functional units is to use a
single bus, as shown below

Input Output Memory Processor

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 Processor Organization
To understand the organization of the CPU, let us consider the requirements placed
on the CPU, the things that it must do:
•Fetch instruction: The CPU reads an instruction from memory.
•Interpret instruction: The instruction is decoded to determine what action is
required.
•Fetch data: The execution of an instruction may require reading data from memory
or an I/O module.
•Process data: The execution of an instruction may require performing some
arithmetic or logical operation on data.
•Write data: The results of an execution may require writing data to memory or an
I/O module.
To do these things, it should be clear that the CPU needs to store some data
temporarily. It must remember the location of the last instruction so that it can
know where to get the next instruction. It needs to store instructions and data
temporar­ily while an instruction is being executed. In other words, the CPU needs a
small internal memory.

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 Fig 1: The CPU with the System Bus

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 Figure 1 is a simplified view of a CPU, indicating its
connection to the rest of the system via the system bus.
Major components of the CPU are an arithmetic and logic
unit (ALU) and a control unit (CU). The ALU does the
actual computation or processing of data.
The con­trol unit controls the movement of data and
instructions into and out of the CPU and controls the
operation of the ALU.
In addition, the figure shows a minimal internal memory,
consisting of a set of storage locations, called registers.

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 Given Figure is a slightly more detailed view of the CPU. The data transfer
and logic control paths are indicated, including an element labeled internal
CPU-bus. This element is needed to transfer data between the various registers
and the ALU because the ALU in fact operates only on data in the internal
CPU mem­ory.

Figure : CPU Internal Structure

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 2. Register Organization
Within the CPU, there is a set of registers that function as a level of
memory above main memory and cache in the hierarchy. The registers
in the CPU perform two roles:
•User-visible registers: These enable the machine- or assembly-
language pro­grammer to minimize main memory references by
optimizing use of registers.
•Control and status registers: These are used by the control unit to
control the operation of the CPU and by privileged, operating system
programs to control the execution of programs.
There is not a clean separation of registers into these two categories.
For example, on some machines the program counter is user visible
(e.g., Pentium), but on many it is not (e.g., PowerPC). For purposes of
the following discussion, how­ever, we will use these categories.

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 2.1 User-Visible Registers
A user-visible register is one that may be referenced by means of the machine
lan­guage that the CPU executes. We can characterize these in the following
categories:
•General purpose
•Data
•Address
•Condition codes
General-purpose registers: can be assigned to a variety of functions by the pro­
grammer. Sometimes their use within the instruction set is orthogonal to the
opera­tion. That is, any general--purpose register can contain the operand for
any opcode. This provides true general-purpose register use. Often, however,
there are restric­tions. For example, there may be dedicated registers for
floating-point and stack operations. In some cases, general-purpose registers
can be used for addressing functions (e.g.. register indirect, displacement). In
other cases, there is a partial or clean sep­aration between data registers and
address registers.

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 Data registers may be used only to hold data and cannot be employed in the
calculation of an operand address.
Address registers may themselves be somewhat general purpose, or they may
be devoted to a particular addressing mode. Examples include the following:
•Segment pointers: In a machine with segmented addressing, a segment
register holds the address of the base of the segment. There may be multiple
registers: for example, one for the operating system and one for the current
process.
•Index registers: These are used for indexed addressing and may be auto-
indexed.
•Stack pointer: If there is user-visible stack addressing, then typically the
stack is in memory and there is a dedicated register that points to the top of
the slack. This allows implicit addressing; that is, push, pop, and other slack in­
structions need not contain an explicit stack operand.

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 2.2 Control and Status Registers
There are a variety of CPU registers that are employed to control the
operation of the CPU. Most of these, on most machines, are not visible to the
user. Some of them may be visible to machine instructions executed in a
control or operating system mode.
Of course, different machines will have different register organizations and
use different terminology. We list here a reasonably complete list of register
types, with a brief description.
Four registers are essential to instruction execution:
•Program counter (PC): Contains the address of an instruction to be fetched.
•Instruction register (IR): Contains the instruction most recently fetched.
•Memory address registers (MAR): Contains the address of a location in
memory.
•Memory buffer register (MBR): Contains a word of data lo be written to
mem­ory or the word most recently read.

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 A number of other registers related to status and control might be found in a
particular CPU design. In addition to the PSW, there may be a pointer to a
block of memory containing additional status information (e.g., process
control blocks).

Example Register Organizations:

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 3. Instruction Cycle
Recall that the instruction cycle includes the following sub-cycles:
•Fetch: Read the next instruction from memory into the CPU.
•Execute: Interpret the opcode and perform the indicated operation.
•Interrupt: If interrupts are enabled and an interrupt has occurred, save the
current process state and service the interrupt.
We are now in a position to elaborate somewhat on the instruction cycle. First,
we must introduce one additional sub-cycle, known as the indirect cycle.

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Department of Computer
 Data Path in a CPU

The CPU can be divided into two sections: the data section
and the control section. The DATA section is also known
as the data path.
BUS: In early computers “BUS” were parallel electrical
wires with multiple hardware connections. Therefore a bus
is a communication system that transfers data between
components inside a computer, or between computers. It
includes hardware components like wires, optical fibers,
etc and software, including communication protocols. The
Registers, ALU, and the interconnecting BUS are
collectively referred to as data paths.

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 Types of the bus are:

1.Address bus: The buses which are used to carry address.

2.Data bus: The buses which are used to carry data.

3.Control bus: If the bus is carrying control signals.

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INPUT/OUTPUT ORGANIZATION

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Accessing I/O Devices

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Engineering, PCCOE
Accessing I/Odevices

Process Memor
or y
Bu
s

I/O vice I/O vic n

de 1 de e

•Multiple I/O devices may be connected to the processor and the memory via a
bus.
• Bus consists of three sets of lines to carry address, data and control signals.
• Each I/O device is assigned an unique address.
• To access an I/O device, the processor places the address on the address lines.
• The device recognizes the address, and responds to the control signals.
 Accessing I/O devices (contd..)

⚫ I/O devices andt h e memor

y mayshare the same addres
s space:
⚫ M e m o r y - m a p p e d I/O.
⚫ A ny m a c h i n e i n s t ru c t i o n that c a n a c c e s s m e m o r y
can be u s e d to t ra n s fe r d a ta to o r f r o m a n I / O d
evice.
⚫

⚫
S i m p l e r software.
I/ O d e v i c e s and the m
e m o r y m a y h a v ed i ff e r e n t a
ddress spaces:
⚫ S p e c i a l i n s t r u c t i o n s t o t r a n s fe r d a t a t o a n d
from I/O devices.
⚫ I / O d e v i c e s m a y h a v e to d e a l with fe w e r a d d
r e s s l ines.
⚫ I / O a d d r e s s l i n e s n e e d n o t b e p hy s i c a l l y s e
p a ra t e
Accessing I/O devices (contd..)
Address
Bu lDinaeat s
s
lCinoens
trol
lines
Address Control Data I/
decoder circuit registers Oi
nerfac
te

Input
device
• I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
• Data register holds the data being transferred to or from the processor.
• Status register holds informati on necessary for the operati on of the I/O device.
• Data and status registers are connected to the data lines, and have
unique addresses.
 Accessing I/O devices (contd..)

⚫ Recall t h a t t h e r a t e o f t r a n s f e r t o a n df r o m
I/O
devices is s l o w e r t h a nt h e s p e e d of t h e
p r o c e s s o r. This creates the need for
mechanisms to synchronize datatrans
fers between them.
⚫ P r o g r a m - c o n t r o l l e d I / O:
⚫ P ro c e s s o r re p e at e d l y m o n i t o r s a status
fl a g to
a c h i e ve t h e n e c e s s a r y sy n c h ro n i za t
ion.
⚫ P ro c e s s o r p o ll s t h e I/ O d e v i c e .
⚫ Tw o other mechanisms used for
synchronizing d a t a t r a n s f e r sb e t w e e n
the processor and memory:
⚫ Interrupts.
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Bus arbitration
⚫ Processor a n d DMA co nt ro l l e r s both
n e e d to in i t i ate d ata t ra n s fe rs o n t
h e b u s a n d a c c e s s m a i n m e m o r y.
⚫ T h e d e v i c e t h at i s a l l o w e d to
i n i ti a t e t r a n s f e r s o n t h e b u s at a n y g i
v e n t i m e i s c a l l e d t h e b u s m a s t e r.
The p r o c e s s b y w h i c h t h e n e x t d e v i c e to b e c
ome the bus m a s t e r is s e l e c t e d a n d bus
m a s t e r s h i p is

⚫
t r a n s f e r r e d t o it i s c a l l e d b u s arbitration .
C e n t r a l i ze d ar bi t rati on:
⚫

⚫
A s i n g l e b u s a r b i te r p e r f o r m s t h e arbitration.
D i s t r i buted ar bi t rati on:
⚫ All d e v i c e s p a r t i cDi pepaat retmi nentthoef Csoeml peuctteiro n
of t h e n e x t bus
 Interface Circuits

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Interface circuits
⚫ I/ O i n t e r f a c ec o n s i s t s o f t h e c i r c u i t r y r e
q u i r e d to c o n n e c t I / O d e v i c e to acom
puter bus.
⚫ S i d e of t h e i n t e r fa c e w h i c h c o n n
e c t s to t h e c o m p u t e r h a s b u s
signals for:
⚫ Ad d re s s ,
⚫ Data
⚫

⚫
C o nt ro l
S i d e of t h e i n t e r fa c e w h i c h con
n e c t s to the I / O device ha
s:
⚫ Data p at h a n d a s s o c i a t e d co nt ro l s to t ra n s fe r d a ta b e t
w e e n t h e i n te r fa c e a n d t h e I/O d e v i c e .
⚫

⚫
T h i s s i d e i s c a l l e d a s a “port ”.
Ports c a n be c l a s s i fi e d i nto two:
⚫ Pa ral l e l port,
 Interface circuits (contd..)
⚫ Paral l e l p o r tt ra n s fe rs d ata in t h e f o r m
of a n u m b e r of bits, n o r m a l l y 8 or 16
to or
fromthe device.
⚫ S e r i a l p o r t t r a n s fe r s and re
c e i v e s d ata o n e bit at a
time.
⚫ P r o c e s s o r c o m m u n i c a t e swi t h
t h e bus i n the same way, w h e t
her it is a
p a ra l l e l p o r t o r a s e r i a l port.
⚫ C o n v e r s i o n f r o m t h e p a ra l l e l to s e r i a l a n d v i c e
v e r s a t a ke s p l a c e i n s i d e t h e i n t e r f a c e c i rc u i t .
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Parallel port
Data

Address
DATAIN Dat
a Encod
Proce R/W eran Keyboar
S
ss or swditche
Master-read I debdouncin
y N Val s
Inpu i g circui
Slave-read
intterfac d t
y
e

• Keyboard is connected to a processor using a parallel port.

• Processor is 32-bits and uses memory-mapped I/O and the
asynchronous bus
protocol.
• On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Serial port
⚫ Serial p is u s e d to conne
ort proces ct t h e to I/O devic
ts roar n s m i s s i oe ns o f d a t at oh at
n e bit
r e qatu iar et i
me.
⚫ S e r i a l p o r t c o m m u n i c a t e s ina
bit -
s e r i a l fa s h i o n on t h e d e v i c e
side a n d bit p a r a l l e l f a s h i
o n o n t h e bus s i de.
⚫ Tr a n s f o r m a t i o n b e t w e e n t h e p a r a l l e l a n d s e r i a
l
formats is a c h i e v e d with shift re g i s te rs
t h a t h a v e p a ra l l e l a c c e s s
capab ility.
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 Serial port (contd..)
⚫ Serial i nt erfaces require fewer wi res, and
hence serial transmission is convenient fo r
c o n n e c t i n g d e v i c e s that are physically
d i stant from t h e c o m p u t e r.

⚫ Speed of transmission of the d ata over

a s e r i a l i n t e r fa c e is k n o w n a s t h e “bit rate”.
⚫ Bit ra te d e p e n d s o n t h e n a t u re of t h e d e v i c e s c o n n e c te
d.
⚫ In o r d e r to a c c o m m o d a t e devices wi t h
a
range ofspeeds, a seri al i nt erface must
be able tou s e a range of clock speeds.

⚫ Several standard serial i nt erfaces have bee

n developed:
⚫ U n i v e r s a l A s y n c h r o n o u s R e c e i v e r Tr a n s m i t t e r (UART) f o r
low- speed serial devices.

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 Standard I/Ointerfaces
⚫ I/ O d e v i c e is connected to a computer usi
n g a n i n t e r fa c e c i r c u i t .

⚫ Do we h a v e to d e s i g n a d i ffe r e n t i n t e r fa c e
fo r
every combination of an I/O device and
a computer?
⚫ A p ra c t i ca l approach is to d e v e l o p standar
d i nt e r fa c e s a n d protocols.
⚫ A personal computer has:
⚫ A motherboard which houses the processor chip, ma
i n m e m o r y a n d s o m e I/O i nte r fa c e s .
⚫ A fe w c o n n e c t o r s i nto w h i c h a d d i t i o n a l i n te r fa c e s c a n
be plugged.
⚫ Processor b u s i s d e fi n e d by the signals on t
he processor chip.
⚫ D e v i c e s w h i c h r e q u i re h i g h - s p e e d c o n n e c t i o n to t h e p r o c e
ssor

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Standard I/O interfaces (contd..)
⚫ A n u m b e r of s t a n d a r d s
h a v e b e e n d e v e l o p e d fo
r the
e x p a n s i o n bus.
⚫ S o m e h a v e e v o l v e d b y d e fa u l t .
⚫ F o r e x a m p l e , I B M ’s I n d u s t r y S t a n d

⚫
a r d A rc h i te c t u re .
Three widely used
bus s ta n d a rd s :
⚫ PCI ( Pe r i p h e ra l C o m p o n e n t I nte
rco n n e c t )
⚫ SCSI (Small Computer System
I n t e r fa c e )
⚫ U S B ( Universal S e r i a l Bus)
Standard I/O interfaces (contd..)

Processor
Main Bridge circuit translates
memory
signals and protocols from
processor bus to PCI bus.
Processor bus

Bridge

PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller Interface

SCSI u
b s IDE
disk
Vide
o
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM Keyboard Game
 PCI Bus
● Peripheral Component Interconnect
⚫ I n t ro d u c e d in 1 9 9 2
⚫ L o w - c o s t bus
⚫ Processor independent
⚫ P l u g - a n d - p l a y ca p a b i l i t y
⚫ I n t o d a y ’s c o m p u t e r s , m o s t m e m o r y t r a n s f e r s i n v o l
v e a burst o f d a ta ra t h e r t
h a n j u st o n e wo rd . T h e PCI i s
designed p r i m a r i l y to s u p p o r t this m o d e of o p e
ra t i o n .
⚫ T h e bus s u p p o r t s t h r e e i n d e p e n d e n t a d d r e s s s p a c
es:
m e m o r y, I/ O, a n d c o n fi g u r a t i o n .
⚫ w ea s s u m e d t h a t t h e m a s t e rm a i n t a i n s t h e a d d r e
ss
i n fo r m a t i o n o n t h e b u s until d a ta t ra n s fe r i s c o m p
leted.
But, t h e ad d r e s s i s needed only
long enough fo r t h e
s l av e to b e s e l e c te d . T h u s , t h e a d d r e s s is n e e d e d
o n t h e b u s fo r o n e c l o c k c y c l e o n l y, f r e e i n g t h e a d
d r eof sComputer
Department s l i n e s to b e u s e d fo r s e n d i n g d a ta in s u b s e q u
 SCSI Bus
⚫ The a c r o n y m S C S I s ta n d s for S m a l l C o m p u t
e r S y s t e m I nte r fa c e .
⚫ It r e f e r s t o a s t a n d a r d b u s d e fi n e d b y t h e
American N a ti o n a l S t a n d a r d s I n sti t u te (ANSI)
⚫ In t h e o r i g i n a l s p e c i fi c a t i o n s o f t h e s t a n d a
r d , d e v i c e ss u c h a s d i s ks a r e c o n n e c t e d to a
computer via a 5 0 - w i r e ca b l e , w h i c h c a n
b e u p to 25meters in l e n gt h a n d
can t ra n s fe r
d a ta at ra te s u p to 5 m e ga b y t e s / s .
⚫ The SCSI bus standard has undergone ma
n y r e v i s i o n s , a n di t s d a t a t r a n s f e r c a p a b i l i t y
has i n c r e a s e d v e r y r a p i d l y, a l m o s t d o u b l i
n g e v e r y two y e a r s .
⚫ SCSI-2 a n d S C S I - 3 h a v e b e e n d e fi n e d ,
and e a c h h a s s e v e r a l o p ti o n s .
 SCSI Bus(Contd.,)
⚫ Devices c o n n e c t e dto t h e S C S I a r e n o t p a r t of t h e a d d r e s
spab c eu so f t h e p r o c e s s o r
⚫
s
T h e S C S I b u s is c o n n e c t e d to t h e p r o c e s s o r bus t h ro u g h a
S C S I c o n t r o l l e r. T h i s c o n t r o l l e r u s e s D M A t o t r a n s fe r d a t a p a
c k e t s f r o m t h e m a i n m e m o r y to t h e d e v i c e , or v i c e v e rs a .
⚫ A p a c ke t m a y c o n ta i n a b l o c k o f data, c o m m a n d s f r o m
t h e p r o c e s s o r t o t h e d e v i c e , o r s ta t u s i n f o r m a t i o n a b o u t t h e
device.
⚫ A co n t ro l l e r c o n n e c t e d to a S C S I bus is o n e of two t y p e s –
a n in i t iator or a target.
⚫ An in i t iator h a s t h e ability to s e l e c t a p a r t i cu l a r ta rget a n d to
s e n d c o m m a n d s s p e c i f y i n g t h e o p e ra t i o n s to b e p e r f o r m e d
. T h e d i s k c o n t r o l l e r o p e r a t e s a s a ta r g e t . It c a r r i e s o u t t h
e c o m m a n d s it r e c e i v e s f r o m t h e initi ator.
⚫ T h e in i t iator e s ta b l i s h e s a l o g i ca l c o n n e c t i o n with t h e i n t
e n d e d target.
⚫ O n c e t h i s c o n n e c t i o n h a s b e e n e s t a b l i s h e d , it c a n b e s u s p e n
ded
a n d re s t o re d as n e e d e d to t ra n s fe r c o m m a n d s a n d b u rsts of
data.
⚫ W h i l e a p a r t i cu l a r c o n n e c t i o n i s s u s p e n d e d , o t h e r d e v i c e
can use the bus
to t ra n s fe r i n fo r m a t i o n .
 SCSI Bus(Contd.,)

⚫ D ata t ra n s fe rs on the SCSI bus a

r e a l w ay s co nt ro l l e d b y t h e ta rget
c o n t r o l l e r.
⚫ To s e n d a command to a t a r g e t ,
an
in i t i ator requests co nt ro l of t h e bus an
d , after winning a r b i t r a ti o n , selects the
co nt ro l l e r wa nt s to communic
it a n d h a t e w i t h co nt ro l
⚫ a
Tnhdens t h e of c ot hn et r obus
ller over
st a r tto
s it. a d a t a t ra
n s fe r o p e ra t i o n to r e c e i v e
a
c o m m a n d f r o m t h e initi ator.
 USB
⚫ U n i ve rs a l Serial Bus ( USB) is a n industr
y standard developed through a
col l aborat i ve effort of several computer
and communication companies,
including Compaq, H e w l e t t - P a c k a r d , Intel, L u c
ent , M i c r o s o ft , N o r t e l
Net wor ks, and Philips.
⚫ Speed
⚫ L o w - s p e e d ( 1 . 5 M b /s )
⚫ F u l l - s p e e d ( 1 2 M b /s )
⚫ H i g h - s p e e d ( 4 8 0 M b /s )

⚫ Port Limitation
⚫ Device Characteri st i cs
⚫ Plug-and-play

Department of Computer
Universal Serial Bus tree structure

Host computer

Root
hub

Hub Hub

Hub I/O I/O I/O I/O

d vice d vice d vice d vice
e e e e

I/O
d vice
I/O
d vice
e e Department of Computer
Universal Serial Bus tree structure
⚫ To a c c o m m o d a t e a l a r g e n u m b e r o f d e v i c e s that
can b e a d d e d o r r e m o v e d at a n y t i m e , t h e U S B
has the tree s t r ucture as shown in t h e
fi g u r e .
⚫ Each n o d e o f t h e t r e e h a s a d e v i c e ca l l e d a
hub, w h i c h acts as an intermediate co
nt ro l po i nt
between t h e h o s t a n d t h e I / O d e v i c e s . At t h e ro o t
of t h e t r e e , a ro o t h u b c o n n e c t st h e e nt i
re t r e e t ot h e h o s t c o m p u t e r. T h e l e a v e s of t h e t r
ee are the I/O
devices b e i n g s e r v e d ( fo r e x a m p l e , k e y b o a
r d , I n t e r n e t c o n n e c t i o n , s p e a k e r, o r d i g i t a l TV)
⚫ In n o r m a l o p e rat i o n , a h u b c o p i e s a m e s s a g
e that it
receives f r o m i ts u p s t r e a m c o n n e c t i o n to
a l l i ts
downstream ports. As a result, a m e s s a g e
s e nt by
the h o s t c o m p u t e r i s b ro a d ca s t to a l l I / O d e v i c e s ,
b u t o n l yt h e a d d r e s s e d d e v i c e will r e s p o n d to that
message. H o w e v e r, a m e s s a g e f r o m a n I / O d e v i c e
i s s e nt o n l y u p s t r e a m to w a r d s t h e
ro o t of t h e tree and
Department of Computer
Memory cells-SRAM and DRAM cells, Internal Organization of
a memory chip, Organization of a memory unit.

UNIT IV: Memory Subsystem

Semiconductor Memory Types
 Semiconductor Memory

RAM
Misnamed as all semiconductor memory is random access
Read/Write
Volatile
Temporary storage
Static or dynamic
Memory Cell Operation
 Dynamic RAM

Bits stored as charge in capacitors

Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
Level of charge determines value
Dynamic RAM Structure
 DRAM Operation

Address line active when bit read or written

Transistor switch closed (current flows)
Write
Voltage to bit line
High for 1 low for 0
Then signal address line
Transfers charge to capacitor
Read
Address line selected
transistor turns on
Charge from capacitor fed via bit line to sense amplifier
Compares with reference value to determine 0 or 1
Capacitor charge must be restored
 Static RAM

Bits stored as on/off switches

No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
Uses flip-flops
 Static RAM Operation

Transistor arrangement gives stable logic state

State 1
C1 high, C2 low
T1 T4 off, T2 T3 on
State 0
C2 high, C1 low
T2 T3 off, T1 T4 on
Address line transistors T5 T6 is switch
Write – apply value to B & compliment to B
Read – value is on line B
 SRAM v DRAM

Both volatile
Power needed to preserve data
Dynamic cell
Simpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units
Static
Faster
Cache
 Read Only Memory (ROM)

Permanent storage
Nonvolatile
Microprogramming (see later)
Library subroutines
Systems programs (BIOS)
Function tables
 Types of ROM

Written during manufacture

Very expensive for small runs
Programmable (once)
PROM
Needs special equipment to program
Read “mostly”
Erasable Programmable (EPROM)
Erased by UV
Electrically Erasable (EEPROM)
Takes much longer to write than read
Flash memory
Erase whole memory electrically
 Organisation in detail

A 16Mbit chip can be organised as 1M of 16 bit words

A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip
1 and so on
A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address
11 pins to address (211=2048)
Adding one more pin doubles range of values so x4 capacity
 Refreshing

Refresh circuit included on chip

Disable chip
Count through rows
Read & Write back
Takes time
Slows down apparent performance
 Synchronous DRAM (SDRAM)

Access is synchronized with an external clock

Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock, CPU knows when data
will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data and fire it out in block
DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)
 Types of External Memory

Magnetic Disk
RAID
Removable
Optical
CD-ROM
CD-Recordable (CD-R)
CD-R/W
DVD
Magnetic Tape