INPUT/OUTPUT ORGANIZATION

Department of Computer
Accessing I/Odevices

Processor Memory

Bus

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the memory via a
bus.
• Bus consists of three sets of lines to carry address, data and control signals.
• Each I/O device is assigned an unique address.
• To access an I/O device, the processor places the address on the address lines.
• The device recognizes the address, and responds to the control signals.
Department of Computer
Accessing I/O devices (contd..)
⚫ I/O d e v i c e sa n d t h e m e m o r y m a y s h
are the same address space:
⚫ M e m o r y - m a p p e d I/O.
⚫ A ny m a c h i n e i n s t ru c t i o n that c a n a c c e s s m e m o r y
can be u s e d to t ra n s fe r d a ta to o r f r o m a n I / O d
evice.
⚫

⚫
S i m p l e r software.
I/ O d e v i c e sa n d t h e m e m o r y m
a y h a v e d i ffe r e n t a d d r e s s s
paces:
⚫ S p e c i a l i n s t ru c t i o n s to t ra n s fe r d a ta to a n d
from I/O devices.
⚫ I / O d e v i c e s m a y h a v e to d e a l with fe w e r a d d
r e s s l ines.
⚫ I / O a d d r e s s l i n e s n e e d n o t b e p hy s i c a l l y s e
p a ra t e
from m e m o r y a d d r e s s l ines.
⚫ I n fa ct, a d d r e s s l i n e s m a y be s h a r e d b e t
Accessing I/O devices (contd..)
Bu
s

Address Control Data I/

decoder circuit registers Oi
nerfac
te

Input
device
• I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
• Data register holds the data being transferred to or from the processor.
• Status register holds informati on necessary for the operati on of the I/O device.
• Data and status registers are connected to the data lines, and have
unique addresses.
•I/O interface circuit coordinatDeespI/aOrttmraennstfoefrsC
 Accessing I/O devices (contd..)
⚫ Recall t h a t t h e r a t e o f t r a n s f e r t o a n df r o m
I/O
devices is s l o w e r t h a n t h e s p e e d of t h e
p r o c e s s o r. This creates the need for
mechanisms to synchronize datatrans
fers between them.
⚫ P r o g r a m - c o n t r o l l e d I / O:
⚫ P ro c e s s o r re p e at e d l y m o n i t o r s a status
fl a g to
a c h i e ve t h e n e c e s s a r y sy n c h ro n i z a t
ion.
⚫ P ro c e s s o r p o l l s t h e I/ O d e v i c e .
⚫ Tw o other mechanisms used for
synchronizing d a t a t r a n s f e r sb e t w e e n
the processor and memory:
⚫ Interrupts. Department of Computer
Bus arbitration
⚫ P r o c e s s o r a n d DMA co nt ro l l e r s b
oth
n e e d to in i t i ate d ata t ra n s fe rs o
n t h e bus and access mai
n m e m o r y.
⚫ T h e d e v i c e that i s a l l o w e d to
⚫ initi
W h eate n t r a nt sh fee r s counr r t h e b u bs u s m aats t e
reenlatinnyq gu i vs eh ne s t i im e isstact ua sl l eas
d t h etr h e
bmu as smt ae sr,t e ar.n o t h e r d e v i bus caacnq u i r
ts
cthis
e status. e
⚫ The p r o c e s s b y w h i c h t h e n e x t d e v i c e to b e c o
me the bus
m a s t e r is s e l e c t e d a n d bus m a s t e r s h i p is

⚫
t r a n s f e r r e d t o it i s c a l l e d b u s a r b i t ra t i o n .
C e n t r a l i ze d a r b i t rati o n :
⚫

⚫
A s i n g l e b u s a r b i t e r p e r f o r m s t h e a r b i t ra t i o n .
D i s t r i buted a r b i t rati o n :
Interface Circuits

Department of Computer
Interface circuits
⚫ I/ O i n t e r f a c e c o n s i s t s o f t h e c i r c u i t r y re
q u i r e d to c o n n e c t a n I / O d e v i c e to
a c o m p u t e r bus.
⚫ S i d e of t h e i n t e r fa c e w h i c h c o n n e
cts to t h e c o m p u t e r h a s b u s
signals for:
⚫ Ad d re s s ,
⚫ Data
⚫

⚫
C o nt ro l
S i d e of t h e i n t e r fa c e w h i c h con
n e c t s to the I / O device ha s
:
⚫ Data p at h a n d a s s o c i a t e d co nt ro l s to t ra n s fe r d a ta b e t
w e e n t h e i n te r fa c e a n d t h e I/O d e v i c e .
⚫
⚫
T h i s s i d e i s c a l l e d a s a “port ”.
Ports c a n be c l a s s i fi e d i nto two:
⚫
Department of Computer
Pa r a l l e l p o r t ,
Interface circuits (contd..)
⚫ Paral l e l p o r t t ra n s fe rs d ata in t h e f o r m
of a n u m b e r of bits, n o r m
ally 8 or 16 to or f r o m t h e d e v i c
e.
⚫ S e r i a l p o r t t ra n s fe rs and re
c e i v e s d ata o n e bit at a
time.
⚫ P r o c e s s o r c o m m u n i c a t e s wi t h
the bus i n the same
way, w h e t h e r it is a
p a ra l l e l p o r t o r a s e r i a l port.
⚫ C o n v e r s i o n f r o m t h e p a ra l l e l to s e r i a l a n d v i c e
v e r s a t a ke s pDepartment
l a c e i n s of
i dComputer
e t h e i n t e r f a c e c i rc u it .
Parallel port
Dat
a Address
DATAIN Data
R/W Encod
SI
Processor er and Keyboard
N
Master-read debuge
Inpu Valid r
Slave-read intterfa
circuit
ce

• Keyboard is connected to a processor using a parallel port.

• Processor is 32-bits and uses memory-mapped I/O and the
asynchronous bus protocol.
• On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
Serial port
⚫ Serial p is u s e d to connec
ort proces t t h e to I/O device
ts roar n s m i s s i os n o f d a t at hoant e rbit
e q uati rae t i
me.
⚫ Serial p o r t c o m m u n i c a t e s ina
bit -
s e r i a l fa s h i o non t h e d e v i c e s i d e
a n d bit p a r a l l e l f a s h i o n o n t
he bus s i de.
⚫ Tr a n s f o r m a t i o n b e t w e e n t h e p a r a l l e l a n d s e r i a l
formats is a c h i e v e d w i t h s h if t r e g i s t e r s
t h a t h a v e p a ra l l e l a c c e s s
capability.
 Serial port (contd..)
⚫ Serial i n t e r fa c e s r e q u i r e fe w e r wi
res, a n d h e n c e s e r i a l t ra n s m i s s i o n
is c o nv e n i e n t fo r c o n n e c t i n g d e
vices that a r e p hy s i c a l l y
d i stant f r o m t h e c o m p u t e r.
⚫ S p e e d of t r a n s m i s s i o n of the d
ata over a s e r i a l i n t e r fa c e
is k n o w n as t h e “bit rate”.
⚫ Bit ra te d e p e n d s o n t h e n a t u re of t h e d e v i c e s c o n n e

⚫
c te d .
In o r d e r to a c c o m m o d a t ed e v i c e swi t
h a
r a n g e of s p e e d s , a s e r i a l i n t e r fa c e
m u s t b e a b l e to u s e a r a n g e
of clock speeds.
 Standard I/O interfaces
⚫ I/ O d e v i c e is c o n n e c t e d to a
computerusing an i n t e r fa c e c i rcuit.
⚫ Do we h a v e to d e s i g na d i ffe r e n t
i n t e r fa c e for
every c o m b i n a t i o n of a n I / O de
vice and a computer?
⚫ A p ra c t i ca l a p p r o a c h is to d e v
elop s t a n d a r d i nt e r fa c e s a n d
p ro to co l s .
⚫ A p e r s o n a l c o m p u t e r ha s :
⚫ A motherboard which houses the processor chip,
m a i n m e m o r y a n d s o m e I / O i n t e r fa c e s .
⚫ A fe w c o n n e c t o r s i nto w h i c h a d d i t i o n a l i n te r fa c e s

⚫
can be plugged.
P r o c e s s o r b u s i s d e fi n e d b y t h e s i g n a l s
on the processor chip.
Standard I/O interfaces (contd..)
⚫ A n u m b e r of s t a n d a r d s
have been developed
fo r the
e x p a n s i o n bus.
⚫ S o m e h a v e e v o l v e d b y d e fa u l t .
⚫ F o r e x a m p l e , I B M ’s I n d u s t r y S t a n d

⚫
a r d A rc h ite c t u re .
T h r e e w i d e l yu s e d b u s s
ta n d a rd s :
⚫ PCI ( Pe r i p h e ra l C o m p o n e n t I nte
rco n n e c t )
⚫ SCSI (Small Computer System
Interface)
⚫ U S B ( U n i v e rs a l S e r i a l B u s )
Standard I/O interfaces (contd..)
Processor
Main Bridge circuit translates
memory
signals and protocols from
processor bus to PCI bus.
Processor
bus

Bridge

PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller Interface

SCSI u
IDE
b s
disk
Vide
o
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM Keyboard Game
PCI Bus
● Peripheral Component Interconnect
⚫ I n t ro d u c e d in 1 9 9 2
⚫ L o w - c o s t bus
⚫ Processor independent
⚫ P l u g - a n d - p l a y ca p a b i l i t y
⚫ I n t o d a y ’s c o m p u t e r s , m o s t m e m o r y t r a n s f e r s i n v o l
v e a b u rs t o f d a ta ra t h e r t
h a n j u st o n e wo rd . T h e PCI i s
designed p r i m a r i l y to s u p p o r t this m o d e of o p e
ra t i o n .
⚫ T h e bus s u p p o r t s t h r e e i n d e p e n d e n t a d d r e s s s p a c
es:
m e m o r y, I/ O, a n d c o n fi g u r a t i o n .
⚫ w ea s s u m e d t h a t t h e m a s t e rm a i n t a i n s t h e a d d r e
ss
i n f o r m a t i o n o n t h e b u s u n t il d a t a t r a n s f e r i s c o m p l
eted.
But, t h e a d d r e s s i s needed only
long enough fo r t h e
s l av e to b e s e l e c te d . T h u s , t h e a d d r e s s is n e e d e d
o n t h e bus fo r o n e c l o c k c y c l e o n l y, f r e e i n g t h e a d
d r e s s l i n e s to b e u s e d fo r s e n d i n g d a ta in s u b s e q u e n
 SCSI
⚫ The
Bus a c r o n y m S C S I s t a n d sf o r S m a l l C o m p u
ter System I nte r fa c e .
⚫ It r e f e r s to a s t a n d a r d bus d e fi n e
d by the
A m e r i c a n Nati ona l S t a n d a r d s Insti tute
(ANSI)
⚫ In t h e o r i g i n a l s p e c i fi c a t i o n s of t h
e s ta n d a rd , d e v i c e s s u c h a s d i s ks a r e
connected to a
c o m p u t e r v i a a 5 0 - w i r e c a b l e ,w h i c h c a n
b e u p to 2 5 meters in l e n gt h a n d
c a n t ra n s fe r
d a ta a t r a t e s u p to 5 m e g a b y t e s / s .
⚫ The SCSIbus standard has un
d e r g o n e m a n y revi s i ons, and i ts
d a ta t ra n s fe r ca p a b i l i t y
has i n c r e a sDepartment
ed ofvComputer
ery r a p i d l y, a l m
 SCSI
⚫
Bus(Contd.,)
Devices
spab
c o n n e c t e dto t h e S C S I
c eu so f t h e p r o c e s s o r
a r e n o t p a r t of t h e a d d r e s

⚫
s
T h e S C S I b u s is c o n n e c t e d to t h e p r o c e s s o r b u s t h ro u g h a
S C S I c o n t r o l l e r. T h i s c o n t r o l l e r u s e s D M A t o t r a n s f e r d a t a p a
c k e t s f r o m t h e m a i n m e m o r y to t h e d e v i c e , or v i c e v e rs a .
⚫ A p a c k e t m a y c o n t a i n a b l o c k o f d a ta , c o m m a n d s f r o m
t h e p r o c e s s o r t o t h e d e v i c e , o r s ta t u s i n f o r m a t i o n a b o u t t h e
device.
⚫ A co n t ro l l e r c o n n e c t e d to a S C S I b u s is o n e of two t y p e s –
a n in i t iator or a target.
⚫ An in i t iator h a s t h e ability to s e l e c t a p a r t i cu l a r ta rget a n d to s
e n d c o m m a n d s s p e c i f y i n g t h e o p e ra t i o n s to b e p e r f o r m e d .
T h e d i s k c o n t r o l l e r o p e r a t e s a s a ta rg e t . It c a r r i e s o u t t h e
c o m m a n d s it r e c e i v e s f r o m t h e initi ator.
⚫ T h e in i t iator e s ta b l i s h e s a l o g i ca l c o n n e c t i o n with t h e i n t
e n d e d target.
⚫ O n c e t h i s c o n n e c t i o n h a s b e e n e s t a b l i s h e d , it c a n b e s u s p e n
ded
a n d re s t o re d as n e e d e d to t ra n s fe r c o m m a n d s a n d b u rsts of
data.
⚫ W h i l e a p a r t i cu l a r c o n n e c t i o n i s s u s p e n d e d , o t h e r d e v i c e
can use the bus
Department
to t ra n s fe r i n fo r m a t i o n . of Computer
 SCSI
⚫Bus(Contd.,)
D ata t ra n s fe rs on t h e SCSI
bus a r e a l w ay s co nt ro l l e d b
y t h e ta rget
controller.
⚫ To s e n d a c o m m a n d to a target,
an
ci noint ti raot ol lr e r r ewqaunet s t s t o ccoomn tmr ou lnoifc at
h e it a nbdu hs t e awni dt h, aco f t entr rowl i n n i n g of
⚫ Ta rn
hbd sra ti tohn e,
ei tn s e l e ccttohsnet r obus
tl hl eer o v e r to
starts it. a d a t a t ra
n s fe r o p e ra t i o n to r e c e i v e
a
c o m m a n d Department f r o m tofhComputer
e initi ator.
USB
⚫ U n i v e r s a l S e r i a lB u s ( USB) i s a n i n d u s
try standard developed through
a
co l l a b o rat i ve e ffo r t of s e v e r a l co
mputer and communication co
mpanies,
i n c l u d i n g C o m p a q ,H ew l ett - Pa c
k a r d , Intel, L u c ent , M i c ro s o ft ,
Nortel
Net wor ks, a n d Philips.
⚫ Speed
⚫ L o w - s p e e d ( 1 . 5 Mb /s)
⚫ F u l l - s p e e d ( 1 2 Mb/s)
⚫
⚫
H i g h - s p e e d ( 4 8 0 Mb/s)
Po r t L i m i tat i o n
⚫ D e v i c e C hDepartment
a r a c t eofrComputer
istics
Universal Serial Bus tree structure

Host computer

Root
hub

Hub Hub

Hub d I/O
vice d I/O
vice d I/O
vice d I/O
vice
e e e e

d I/O
vice d I/O
vice
e e Department of Computer
Universal Serial Bus tree structure
⚫ To a c c o m m o d a t e a l a r g e n u m b e r o f d e v i c e sthat
can b e a d d e d o r r e m o v e d at a n y t i m e , the
U S B h a s t h e t r e e s t r ucture as s h o w n
i n t h e fi g u r e .
⚫ Each node ofthe tree has a device
c a l l e d ah u b , w h i c h a c t s a s a n i n t e r m e d i a t e
co nt ro l po i nt
b e t w e e n t h e h o s t a n dt h e I / O d e v i c e s . At t h e ro o
t of t h e t r e e , a r o o t h u b connects the
e nt i r e t r e e to t h e h o s t c o m p u t e r.
The l e a v e s of t h et r e e a r e t h e I / O
d e v i c e s being s e r v e d ( for e x a m p l
e, k e y b o a r d , I nt e r n e t co n n e

⚫ In n o r m a l
ction, s p e a ke r, o r d i g i t a l TV)
o p e rat i o n , a hub c o p i e s
a message that it
r e c e i v e s f r o m i ts u p s t r e a m co
n n e c t i o n to a l l i ts
d o w n s t r e a m p o r t s . A s a re s u l t , a m e s s a g e
s e nt by
the h o s t c o m p u t e ri s b r o a d c a s t to all I/O de
v i c e s ,b u t o n l y the addressed device