Scribd
Upload
4 views14 pages

Experiment 2

Uploaded by

pilawak670
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
4 views14 pages

Experiment 2

Uploaded by

pilawak670
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 14

Experiment 2

Memory Blocks and the CLOCK_50 Oscillator


Decoder Code: decoder.txt
RAM
Ways to describe a Memory:

 1. IP Cataloge(predefined module)

 2.define the memory as a multidimensional array.

reg [3:0] memory_array [31:0];


 The Cyclone V FPGA on the DE0-CV and DE1-SoC boards contain dedicated memory
resources called M10K blocks, and the Cyclone IV on the DE2-115 contain dedicated
memory resources called M9K blocks. Each M10K block contains 10240 memory bits,
and each M9K block contains 9216 memory bits. Both M10K and M9k blocks can be
configured to implement memories of various sizes. A common term used to specify
the size of a memory is its aspect ratio, which gives the depth in words and the width in
bits (depth x width).
 Blocks includes registers that can be used to
synchronize all of the input and output signals to a clock input.
The registers on the input ports must always be used,
and the registers on the output ports are optional.

32X4 means the memory contains 32 registers ,


and the registers are 4 bits wide.
*2^n=32 , n address buss

 reg [3:0] memory_array [31:0];


Part1:

 Create a Verilog file that instantiates the ram32x4 module and that includes the
required input and output pins on your DE-series board. Use slide switches SW3:0 to
provide input data for the RAM, and use switches switches SW8:4 to specify the
address. Use SW9 as the Write signal and use KEY0 as the Clock input. Show the
address value on the 7-segment displays HEX5:4, show the data being input to the
memory on HEX2, and show the data read out of the memory on HEX0.

part1.v
Part2:

 Instead of creating a memory module subcircuit by using the IP Catalog, you should
implement the required memory by specifying its structure in Verilog code by defining
the memory as a multidimensional array. A 32 x 4 array.
CLOCK_50 Signal

 the Altera® DE-series boards include an on-board oscillator


which generates a 50 MHz clock .
 The 50 MHz clocks can be used directly to clock the registers in the FPGA.
However, sometimes different clocks are desired either internally to run the circuit faster or
slower, or externally for particular peripherals.
Please see the code shown below which creates 1 HZ signal from the 50 _MHZ signal.
Part3:

 Design and implement a circuit that successively flashes digits 0 through 9 on the 7-
segment display HEX0. Each digit should be displayed for about one second. Use a
counter to determine the one second intervals. The counter should be incremented by
the 50-MHz clock signal provided on the DE2-series board. Do not derive any other
clock signals in your design–make sure that all flip-flops in your circuit are clocked
directly by the 50-MHz clock signal.
Your output should be….

You might also like