MICROPROCE

SSOR AND ITS

ARCHITECTU
RE
BY
DR. RAM PAL SINGH
THE PROGRAMMING
MODEL
 Before a program is written or any instruction investigated,
the internal configuration of the microprocessor must be
known.
 In a multiple core microprocessor each core contains the
same programming model.
 Each core runs a separate task or thread simultaneously.
 8086 through Core2 considered program visible
 These registers are used during programming and are specified
by the instructions.
 Other registers considered to be program invisible
 They are not addressable directly during applications
programming but may be used indirectly in system
programming.
 80286 and above contain program-invisible registers to
control and operate protected memory and other features
of the microprocessor.

 80386 through Core2 microprocessors contain full 32-bit

internal architectures.

 8086 through the 80286 are fully upward compatible to

the 80386 through Core2.
The programming model of the 8086 through the Core2
Microprocessor including the 32-bit extensions.
 REGISTERS
 There are 3 types of registers:
1. Multipurpose Registers
2. Special Purpose Registers
3. Segment Registers
 The programming model contains 8-, 16-, and 32-bit registers.
 The 8-bit registers are :
 AH, AL, BH, BL, CH, CL, DH, and DL
 16-bit registers are :
 AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS, CS, DS, ES, SS, FS,
and GS.
 The extended 32-bit registers are :
 EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI, EIP, and EFLAGS.
 The 64-bit registers are designated as :
 RAX, RBX, RCX, RDX, RSP, RBP & so on..
 MULTIPURPOSE
REGISTERS
 RAX (accumulator) :
 RAX is referenced as a 64-bit register (RAX),
 32-bit register(EAX),
 16-bit register (AX), or
 as either of two 8-bit registers (AH and AL).
 The accumulator is used for instructions such as multiplication,
division, and some of the adjustment instructions.
 In the 64-bit Pentium 4 and Core2, RAX holds a 64-bit offset
address, which allows 1T (terra) byte of memory to be accessed
through a 40-bit address bus.
 In the future, Intel plans to expand the address bus to 52 bits to
address 4P (peta) bytes of memory.
 RBX (base index):
 RBX , addressable as RBX, EBX, BX, BH, or BL.
 The BX register (base index) sometimes holds the offset address
of a location in the memory system in all versions of the
microprocessor.
 In the 80386 and above, EBX also can address memory data.
 In the 64-bit Pentium 4 and Core2, RBX can also address
memory data.

 RCX (count):
 RCX addressable as RCX, ECX, CX, CH, or CL,.
 It is a general-purpose register that also holds the count for
various instructions.
 In the 80386 and above, the ECX register also can hold the offset
address of memory data.
 In the 64-bit Pentium 4, RCX can also address memory data.
 Instructions that use a count are the repeated string instructions
(REP/REPE/REPNE); and shift, rotate, and LOOP/LOOPD
 RDX (data) :
 RDX is addressable as RDX, EDX, DX, DH, or DL,.
 It is a general-purpose register that holds a part of the result
from a multiplication or part of the dividend before a division.
 In the 80386 and above, this register can also address memory
data.

 RBP(base pointer) :
 RBP is addressable as RBP, EBP, or BP.
 It points to a memory location in all versions of the
microprocessor for memory data transfers.

 RDI (destination index) :

 RDI, which is addressable as RDI, EDI, or DI.
 It addresses string destination data for the string instructions.
 RSI (source index):
 RSI is used as RSI, ESI, or SI.
 The source index register often addresses source string data for
the string instructions.
 RSI also functions as a general-purpose register.
 As a 16-bit register, it is addressed as SI;
 As a 32-bit register, it is addressed as ESI; and
 As a 64-bit register, it is addressed as RSI.

 R8 through R15 :
 These registers are only found in the Pentium 4 and Core2 if
64-bit extensions are enabled.
 Most applications will not use these registers until 64-bit
processors are common.
 Legacy software doesn't access R8 through R15.
SPECIAL-PURPOSE REGISTERS
 The special-purpose registers include:
 RIP,
 RSP and
 RFLAGS.

 RIP (instruction pointer) :

 RIP addresses the next instruction in a section of memory
defined as a code segment.
 This register is IP (16 bits) when the microprocessor operates
in the real mode
 EIP (32 bits) when the 80386 and above operate in the
protected mode.
 (8086, 8088, and 80286 do not contain an EIP register and
only the 80286 and above operate in the protected mode.)
 RSP (stack pointer) :
 RSP addresses an area of memory called the stack. The stack memory
stores data through this pointer.
 This register is referred to as SP if used as a 16-bit register and ESP if
referred to as a 32-bit register.

 RFLAGS :
 RFLAGS indicate the condition of the microprocessor and control its
operation.
 The 8086–80286 contain a FLAG register (16 bits) and the 80386 and
above contain an EFLAG register (32-bit extended flag register).
 The 64-bit RFLAGS contain the EFLAG register, which is unchanged
in the 64-bit version.
 RFLAGS
 C (carry) :
 Carry holds the carry after addition or the borrow after
subtraction.
 Sometimes for DOS function calls the carry flag also indicates
error conditions.

 P (parity) :
 Parity is a logic 0 for odd parity and a logic 1 for even parity.
 Parity is the count of ones in a number expressed as even or odd.

 A (auxiliary carry) :
 The auxiliary carry holds the carry (half-carry) after addition or
the borrow after subtraction between bit positions 3 and 4 of the
result.
 Z (zero) :
 The zero flag shows that the result of an arithmetic or logic operation
is zero.
 If , Z=1, the result is zero; if Z=0 , the result is not zero.

 S (sign) :
 The sign flag holds the arithmetic sign of the result after an
arithmetic or logic instruction executes.
 If S=1, the sign bit (leftmost bit of a number) is set or negative; if
S=0, the sign bit is cleared or positive.

 T (trap) :
 The trap flag enables trapping through an on-chip debugging feature.
 If the T flag is enabled (1), the microprocessor interrupts the flow of
the program on conditions as indicated by the debug registers and
control registers.
 If the T flag is a logic 0, the trapping (debugging) feature is disabled.
 The Visual C++ debugging tool uses the trap feature and debug
registers to debug faulty software.
 I (interrupt) :
 The interrupt flag controls the operation of the INTR (interrupt
request) input pin.
 If I=1, the INTR pin is enabled; if I=0, the INTR pin is
disabled.
 The state of the I flag bit is controlled by the STI (set I flag)
and CLI (clear I flag) instructions.

 D (direction) :
 The direction flag selects either the increment or decrement
mode.
 If D=1, the registers are automatically decremented; if D=0,
the registers are automatically incremented.
 The D flag is set with the STD (set direction) and cleared with
the CLD (clear direction) instructions.
 O (overflow) :
 Overflows occur when signed numbers are added or subtracted.
 An overflow indicates that the result has exceeded the capacity
of the machine.
 For unsigned operations, the overflow flag is ignored.

 IOPL (I/O privilege level) :

 IOPL is used in protected mode operation to select the privilege
level for I/O devices.
 If the current privilege level is higher or more trusted than the
IOPL, I/O executes without hindrance.
 If the IOPL is lower than the current privilege level, an interrupt
occurs, causing execution to suspend.
 An IOPL of 00 is the highest or most trusted and an IOPL of 11
is the lowest or least trusted.
 NT (nested task) :
 The nested task flag indicates that the current task is nested
within another task in protected mode operation.

 RF (resume) :
 The resume flag is used with debugging to control the
resumption of execution after the next instruction.

 VM (virtual mode) :
 The VM flag bit selects virtual mode operation in a protected
mode system.
 A virtual mode system allows multiple DOS memory
partitions that are 1M byte in length to coexist in the memory
system.

 VIF (virtual interrupt) :

 The VIF is a copy of the interrupt flag bit available to the
Pentium–Pentium 4 microprocessors.
 AC (alignment check) :
 The alignment check flag bit activates if a word or doubleword is
addressed on a non-word or non-doubleword boundary.
 Only the 80486SX microprocessor contains the alignment check bit.

 VIP (Virtual Pending Interrupt):

 VIP provides information about a virtual mode interrupt for the
Pentium–Pentium 4 microprocessors.
 This is used in multitasking environments to provide the operating
system with virtual interrupt flags and interrupt pending
information.

 ID (identification) :
 The ID flag indicates that the Pentium–Pentium 4 microprocessors
support the CPUID instruction.
 The CPUID instruction provides the system with information about
the Pentium microprocessor, such as its version number and
manufacturer.
SEGMENT REGISTERS
 Segment registers include:
 CS (Code Segment) ,
 DS (Data Segment) ,
 ES (Extra Segment) ,
 SS (Stack Segment) ,
 FS and GS (Supplement Segment Registers)

 These additonal registers, generate memory addresses when

combined with other registers in the microprocessor.

 There are either four or six segment registers in various versions

of the microprocessor.

 A segment register functions differently in the real mode when

 CS (code) :
 The code segment is a section of memory that holds the code
(programs and procedures) used by the microprocessor.
 The code segment register defines the starting address of the section
of memory holding code.
 In real mode operation, it defines the start of a 64Kbyte section of
memory,
 In protected mode, it selects a descriptor that describes the starting
address, length of a section of memory holding code & access rights.
 In protected mode, it defines the starting of 4Gbyte section of
memory.
 DS (data) :
 The data segment is a section of memory that contains most data used
by a program.
 Data are accessed in the data segment by an offset address.
 ES (extra) :
 The extra segment is an additional data segment that is used
by some of the string instructions to hold destination data.

 SS (stack) :
 The stack segment defines the area of memory used for the
stack.
 The stack entry point is determined by the stack segment and
stack pointer registers.

 FS and GS :
 The FS and GS segments are supplemental segment registers
available in the 80386–Core2 microprocessors.
 They allow two additional memory segments for access by
programs.
REAL MODE MEMORY
ADDRESSING
 Real Memory- The first 1M byte of memory(00000H-
FFFFFH)
(Also called Conventional memory, or DOS memory).

FFFFFH

00000H
 Real Mode operation- It allows the microprocessor to address
only the first 1M byte of memory space.
 Only 8086 and 8088 operate exclusively on real mode.
 SEGMENTS AND
OFFSETS
 Segments in real mode always have a length of 64K bytes.
 Real mode segments can begin only at a 16-byte boundary in
the memory system, known as paragraph.
 To access a memory location in real-mode

Memory address = segment address + offset address(or

displacement)
where
segment address : defines the beginning address
of 64K-byte memory segment.
offset address : selects any location within the
segment.
Segment:

Beginning address = 10000H

Ending address = 1FFFFH

The figure explains real-mode

addressing scheme.
 In the previous example, the segment register contains 1000H,
yet it addresses 10000H because in real mode, each segment
register is internally appended with a 0H on the rightmost end.

 This forms a 20-bit address and hence, the microprocessor

generates a 20-bit address to access a location within first 1M
of memory.

 If the beginning address is known, we can calculate the ending

address of a segment by adding FFFFH.
 In 80286 and 80386 through the Pentium 4, an extra 64K
minus 16 bytes is addressable when the segment address is
FFFFH.

 This area of memory (0FFFF0H-10FFEFH) is referred to as

high memory.

 When address generated has segment address= FFFFH, pin

A20 is enabled while adding the offset.

 Example – Segment address = FFFFH i.e. FFFF0H

Offset address = 4000H
Then, the address generated is 103FF0H.
If A20 is not supported, the address generated is 03FF0H.
DEFAULT SEGMENTS AND
OFFSET REGISTERS

Default 16-bit segment and offset combinations

Default 32-bit segment and offset combinations.
 PLACEMENT OF MEMORY
SEGMENTS

 8086- 80286 allow four memory segments and 80386- Core2

allow six memory segments.

 These segments can touch or even overlap if 64K bytes of

memory are not required for a segment.

 A program can have more than four segments but can access
only four or six segments at a time.
The figure shows a system that contains four memory segments.
RELOCATION IN SEGMENT AND
OFFSET ADDRESSING SCHEME
 This complicated scheme of segment plus offset addressing
allows DOS programs to be relocated in the memory system.
It also allows programs written to function in the real mode
to operate in a protected mode system.

 A relocatable program is one that can be placed into any

area of memory and executed without change.
 Relocatable data are data that can be placed in any area of
memory and used without any change to the program.

 The segment and offset addressing scheme allows both

programs and data to be relocated without changing a thing
in a program or data.

 This is ideal for use in a general-purpose computer system in

which not all machines contain the same memory areas.

 The personal computer memory structure is different from

machine to machine, requiring relocatable software and data.
 Because memory is addressed within a segment by an offset
address, the memory segment can be moved to any place in
the memory system without changing any of the offset
addresses.

 This is accomplished by moving the entire program, as a

block, to a new area and then changing only the contents of
the segment registers.

 If an instruction is 4 bytes above the start of the segment, its

offset address is 4. If the entire program is moved to a new
area of memory, this offset address of 4 still points to 4 bytes
above the start of the segment. Only the contents of the
segment register must be changed to address the program in
the new area of memory.
 PROTECTED MODE MEMORY
ADDRESSING
 Protected mode memory addressing (80286 and above)
allows access to data and programs located above the first 1M
byte of memory, as well as within the first 1M byte of
memory.

 Addressing this extended section of the memory system

requires a change to the segment plus an offset addressing
scheme used with real mode memory addressing.

 When data and programs are addressed in extended memory,

the offset address is still used to access information located
within the memory segment.
 One difference is that the segment address, as discussed with
real mode memory addressing, is no longer present in the
protected mode. In place of the segment address, the segment
register contains a selector that selects a descriptor from a
descriptor table.

 The descriptor describes the memory segment’s location,

length, and access rights. Because the segment register and
offset address still access memory, protected mode instructions
are identical to real mode instructions.

 In fact, most programs written to function in the real mode

will function without change in the protected mode.
SELECTORS & DESCRIPTORS

 The selector, located in the segment register, selects one

of 8192 descriptors from one of two tables of
descriptors.

 The descriptor describes the location, length, and access

rights of the segment of memory. Indirectly, the segment
register still selects a memory segment, but not directly
as in the real mode.

 There are two descriptor tables used with the segment

registers: one contains global descriptors and the other
contains local descriptors.
 The global descriptors (system descriptor) contain
segment definitions that apply to all programs, whereas the
local descriptors(application descriptors) are usually
unique to an application.

 Each descriptor table contains 8192 descriptors, so a total of

16,384 total descriptors are available to an application at any
time. Because the descriptor describes a memory segment,
this allows up to 16,384 memory segments to be described
for each application. Since a memory segment can be up to
4G bytes in length, this means that an application could have
access to 4G x 16,384 bytes of memory or 64T bytes.
 The segment limit contains the last offset address found in a
segment. For example, if a segment begins at memory
location F00000H and ends at location F000FFH, the base
address is F00000H and the limit is FFH. For the 80286
microprocessor, the base address is F00000H and the limit is
00FFH.

 For the 80386 and above, the base address is 00F00000H and
the limit is 000FFH.
 THE G-BIT

 There is another feature found in the 80386 through the

Pentium 4 descriptor that is not found in the 80286
descriptor:
 the G bit, or granularity bit. If G=0, the limit specifies a segment
limit of 00000H to FFFFFH. If G=1 , the value of the limit is
multiplied by 4K bytes (appended with FFFH). The limit is then
00000FFFFH to FFFFFFFFH, if G=1. This allows a segment
length of 4K to 4G bytes in steps of 4K bytes. The reason that the
segment length is 64K bytes in the 80286 is that the offset address
is always 16 bits because of its 16-bit internal architecture.
 AV BIT
 In the 80386 and above descriptor, is used to indicate that the
segment is available (AV = 1 ) or not available (AV = 0 ).
 D BIT

 The D bit indicates how the 80386 through the Core2

instructions access register and memory data in the
protected or real mode.

 If D = 0, the instructions are 16-bit instructions. This

mode is often called DOS mode.

 If D = 1 , the instructions are 32-bit instructions.

 ACCESS RIGHTS BYTE
 It controls access to the protected mode segment. This
byte describes how the segment functions in the system.

 It allows complete control over the segment. If the

segment grows beyond its limit, the microprocessor’s
operating system program is interrupted, indicating a
general protection fault.
HOW THE SEGMENT REGISTER FUNCTIONS
IN THE PROTECTED MODE SYSTEM?
 The 13-bit selector chooses one of the 8192 descriptors from
the descriptor table.

 The TI bit selects either the global descriptor table (TI = 0) or

the local descriptor table (TI = 1 ).

 The requested privilege level (RPL) requests the access

privilege level of a memory segment.

 The highest privilege level is 00 and the lowest is 11. Privilege

levels are used in multiuser environments.
 PROGRAM-INVISIBLE REGISTERS

 The global and local descriptor tables are found in the

memory system. In order to access and specify the
address of these tables, the 80286–Core2 contain
program-invisible registers. The program-invisible
registers are not directly addressed by software.

 These registers control the microprocessor when

operated in protected mode.
 The GDTR (global descriptor table register) and IDTR
(interrupt descriptor table register) contain the base address
of the descriptor table and its limit. The limit of each descriptor
table is 16 bits because the maximum table length is 64K bytes.
When the protected mode operation is desired, the address of
the global descriptor table and its limit are loaded into the
GDTR.

 The location of the local descriptor table is selected from the

global descriptor table. One of the global descriptors is set up
to address the local descriptor table.
 To access the local descriptor table, the LDTR (local
descriptor table register) is loaded with a selector, This
selector accesses the global descriptor table and loads the
address, limit, and access rights of the local descriptor table
into the cache portion of the LDTR.

 The TR (task register) holds a selector, which accesses a

descriptor that defines a task. A task is most often a procedure
or application program.