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Verilog HDL

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Dhamodharan Srinivasan
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14 views22 pages

Verilog HDL

Uploaded by

Dhamodharan Srinivasan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VERILOG HDL

Book:

Verilog HDL – A guide to Digital Design and Synthesis

by
Samir Palitkar
HDL
HDL  Hardware Description Language

Verilog VHDL

Verilog:

 RTL (Register Transfer Level) description not depend on


fabrication tech.

 Easy identification & rectification of bugs.

 Comments.
VERILOG HDL
 Module:
 Basic Building Block
 Provides necessary functionality to higher
level blocks

 Syntax:

module <module_name> (< module_terminal_list>)


.
<module_internal>
.
endmodule
VERILOG HDL
 Levels of Abstraction:

Dataflow Level

Behavioral (or) Algorithmic Level

Structural (or) Gate Level

Switch Level
VERILOG HDL
 Comments:

// Single line comments

/* Multiple line comments */


VERILOG HDL
 Number Specification:
1. Sized numbers:-
Syntax:

<size> ’ <base format><number>

0 to 9 and a to f

Binary (b or B)
Decimal(d or D)
Octal (o or O)
Hexadecimal (h or H)

Specifies no. of bit ( only in decimal)


Example:
4’b1010 12’habc 16’d255
Example:

4’b1010 12’habc 16’d255


VERILOG HDL
 Data Types:
1. Nets:-

wire a;
wire a, b;
wire a = 1’b0;

2.Register:-

reg a,b;
VERILOG HDL
3. Vectors:-

wire [7:0] a;

reg [31:0] addrs;

4. Integer:-
integer count = - 4;
integer data = 10;
VERILOG HDL
5. Real:-

real data;
data = 4e6
(or)
data = 6.234
6. Array:-

wire [3:0] a [0:7];

integer [5:0] data [0:10];


GATE LEVEL MODELING
Module fulladd (sum, cout, a, b, cin);
output sum, cout;
input a, b, cin;
wire g0, g1, g2;

xor ( sum, a, b, cin);


and (g0, a, b);
and (g1, b, cin);
and (g2, a, cin);
or (cout, g0, g1, g2);

endmodule
GATE LEVEL MODELING
Module fullsub (diff, bout, x, y, bin);
output diff, bout;
input x, y, bin;
wire g0, g1, g2, h0;

xor ( diff, x, y, bin);


not ( h0, x);
and (g0, h0, y);
and (g1, y, bin);
and (g2, h0, bin);
or (bout, g0, g1, g2);

endmodule
GATE LEVEL MODELING
Module 4bitPA (s, cout, a, b, cin);
output [3:0] s;
output cout;
input [3:0] a, b;
input cin;
wire c0, c1, c2;

fulladd fa0 ( s[0], c0, a[0], b[0], cin);


fulladd fa1 ( s[1], c1, a[1], b[1], c0);
fulladd fa2 ( s[2], c2, a[2], b[2], c1);
fulladd fa3 ( s[3], cout, a[3], b[3], c2);

endmodule
DATA FLOW MODELING
DATA FLOW MODELING
DATA FLOW MODELING
1. Arithmetic:-

% - modulus  result is the remainder


5%21
-7 % 3  1
9 % -6  3

Use Negative sign only in integer and real values.


-5, -40.12
DATA FLOW MODELING
2. Logical:
DATA FLOW MODELING
3. Relational:-
DATA FLOW MODELING
4. Equality:-

a = 2’b00; b = 2’b10; c= 2’b01; d= 2’b1x; e = 2’b1x

a==b  0; a==c 1; b==d  x; d==e x


DATA FLOW MODELING
5. Bitwise:-
DATA FLOW MODELING
7. Shift:-

x = 4’b1010

y = x>>2  y = 0010

y = x<<1  y = 0100
DATA FLOW MODELING
8. Concatenation:-

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