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Lecture 19marked

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0% found this document useful (0 votes)
33 views16 pages

Lecture 19marked

Uploaded by

Sindhu Ojha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 19

ANNOUNCEMENTS
• For Problem 4 of HW10, use VDD = 1.8V and VTH = 0.4V
• Note: Midterm #2 will be held on Thursday 11/15

OUTLINE
• Common-gate stage
• Source follower

Reading: Chapter 7.3-7.4

EE105 Fall 2007 Lecture 19, Slide 1 Prof. Liu, UC Berkeley


Diode-Connected MOSFETs
Diode-connected NMOSFET Diode-connected PMOSFET

1 1
RX  ro1 RY  ro 2
g m1 gm2

Small-signal analysis circuit Small-signal analysis circuit

• Note that the small-signal model of a PMOSFET is identical to


that of an NMOSFET
EE105 Fall 2007 Lecture 19, Slide 2 Prof. Liu, UC Berkeley
Summary of MOSFET Impedances
• Looking into • Looking into • Looking into the
the gate, the the drain, the source, the
impedance is impedance is impedance is 1/gm
infinite (∞). ro if the gate in parallel with ro if
and source the gate and drain
are (ac) are (ac) grounded.
grounded.

EE105 Fall 2007 Lecture 19, Slide 3 Prof. Liu, UC Berkeley


Common-Gate Amplifier Stage
• An increase in Vin decreases VGS and hence decreases ID.
The voltage drop across RD decreases  Vout increases
The small-signal voltage gain (Av) is positive.

Av  g m RD

EE105 Fall 2007 Lecture 19, Slide 4 Prof. Liu, UC Berkeley


Operation in Saturation Region
• For M1 to operate in saturation, Vout cannot fall below Vb-VTH.
 Trade-off between headroom and voltage gain.

EE105 Fall 2007 Lecture 19, Slide 5 Prof. Liu, UC Berkeley


I/O Impedances of CG Stage ( = 0)
Small-signal analysis circuit for Small-signal analysis circuit for
determining input resistance, Rin determining output resistance, Rout

1
Rin  Rout  RD
gm
EE105 Fall 2007 Lecture 19, Slide 6 Prof. Liu, UC Berkeley
CG Stage with Source Resistance

Small-signal equivalent
circuit seen at input 1
gm
vX  vin
1
RS 
gm

For= 0:
vout vout v X 1 RD
   g m RD  Av 
vin v X vin g m RS  1 1
 RS
gm
EE105 Fall 2007 Lecture 19, Slide 7 Prof. Liu, UC Berkeley
• The output impedance of a CG stage with source resistance is
identical to that of CS stage with degeneration.
Small-signal analysis circuit for
determining output resistance, Rout

Rout  rO 1  g m RS   RS  1  g m rO RS  rO
EE105 Fall 2007 Lecture 19, Slide 8 Prof. Liu, UC Berkeley
CG Stage with Biasing
• R1 and R2 establish the gate bias voltage.
• R3 provides a path for the bias current of M1 to flow.

vout R3 || 1 / g m 
  g m RD
vin R3 || 1 / g m   RS

EE105 Fall 2007 Lecture 19, Slide 9 Prof. Liu, UC Berkeley


CG Stage with Gate Resistance
• For low signal frequencies, the gate conducts no current.
 Gate resistance does not affect the gain or I/O impedances.

EE105 Fall 2007 Lecture 19, Slide 10 Prof. Liu, UC Berkeley


CG Stage Example
Small-signal equivalent Small-signal equivalent
circuit seen at input circuit seen at output
1 1  1 
Rout1  g m1rO1  RS   rO1
g m1 g m 2 1  gm2 
vX  vin  vin
1 1 1  g m1  g m 2 RS
 RS
g m1 g m 2

vout v X g m1 RD   1  
Av    Rout   g m1rO1  || RS   rO1  || RD
v X vin 1  g m1  g m 2 RS   gm2  
EE105 Fall 2007 Lecture 19, Slide 11 Prof. Liu, UC Berkeley
Source Follower Stage
vout rO || RL
Av   1
vin 1  r || R
O L
gm
Small-signal analysis circuit for
determining voltage gain, Av Equivalent circuit

vout  g m v1 ro RL 
vin  v1  vout
 g m vin  vout ro RL 
EE105 Fall 2007 Lecture 19, Slide 12 Prof. Liu, UC Berkeley
Source Follower Example
• In this example, M2 acts as a current source.

rO1 || rO 2
Av 
1
 rO1 || rO 2
g m1
EE105 Fall 2007 Lecture 19, Slide 13 Prof. Liu, UC Berkeley
Rout of Source Follower
• The output impedance of a source follower is relatively low,
whereas the input impedance is infinite (at low frequencies);
thus, it is useful as a voltage buffer.
Small-signal analysis circuit for
determining output resistance, Rout

1 1
Rout  || rO || RL  || RL
gm gm

EE105 Fall 2007 Lecture 19, Slide 14 Prof. Liu, UC Berkeley


Source Follower with Biasing
• RG sets the gate voltage to VDD; RS sets the drain current.
(Solve the quadratic equation to obtain the value of ID.)

Assuming  = 0:
1 W
I D   nCox VDD  I D RS  VTH 
2

2 L

EE105 Fall 2007 Lecture 19, Slide 15 Prof. Liu, UC Berkeley


Supply-Independent Biasing
• If Rs is replaced by a current source, the drain current ID
becomes independent of the supply voltage VDD.

EE105 Fall 2007 Lecture 19, Slide 16 Prof. Liu, UC Berkeley

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