LECTURE 4

THE CENTRAL PROCESSING

UNIT

1
 Introduction
The Architect views the machine as a collection of functional units and
their interconnection
The functional units include subsystems such as: -
 Central Processing Unit (CPU)
 The system Memory, which might include high-speed
semiconductor Random Access Memory (RAM), as well as disk
and tape drives
 input and output equipments e.g Keyboard and Printers
All these functional units are interconnected by buses which are data
pathways over which information passes.

2
 Structure of Von Neumann – Revisited

3
 Central Processing Unit (CPU)
Is the heart of any computer system
This unit is also called as the Instruction Set Processor
(ISP)
Controls the operation of the entire system, performs
the arithmetic and logic operations
It stores and retrieves instructions and data in a main
memory

4
 CPU cont…
The Control Unit: -
 Fetches these instructions from memory, decode them,
and directs the system to execute the operations
indicated by the instructions
 Communicates with the output devices to transfer results
from storage to the output device
 Communicates with the input devices in order to transfer
program instructions and data into storage

5
 CPU cont…
Arithmetic Logic Unit (ALU): -
 Carries all arithmetic and logic operations
 It contains a great deal of mathematical structure
CPU works at a very high speed measured in MHZ (Mega
Hertz)

6
 CPU Internal Structure

7
 Registers
CPU uses Registers as its working space (temporary
storage)
Number and function vary between processor designs
User Visible Registers are: -
 General Purpose Registers: Accumulator (a), Base (b),
Control (c) and Data (D)
 Data Registers (D7 – D0)
 Address Registers (A7 – A0)
 Condition Codes Registers

8
 Registers cont…
Control & Status Registers
 Program Counter
 Instruction Decoding Register
 Memory Address Register
 Memory Buffer Register
Status Registers are also called Flag Registers

9
 Registers cont…
The set of registers within the CPU represents the
top level of the memory hierarchy inside the computer
system
- User visible registers: can be accessed by assembly
language programmers.
- Control and Status registers: used by the Control
Unit to control the operation of the CPU; not directly
accessible by the programmer.

10
 User-visible Registers

Categories of User-visible registers

 General Purpose can be assigned to a variety of functions
by the programmer.
 Data registers are used to hold only the data.
 Address registers hold the address. This may be
categorized as segment, index and stack.
 Condition Codes registers: these hold the condition
codes(flags).
Condition codes are bits set by CPU hardware as a result of
operations.
11
 Registers cont…
 Common fields or flags contained include:
 Sign - sign bit of last arithmetic operation
 Zero - set when result of last arithmetic operation is
0
 Carry - set if last operation resulted in a carry into or
borrow out of a high-order bit
 Equal - set if a logical compare result is equality
 Overflow - set when last arithmetic operation caused
overflow
12
 Registers cont…
 Interrupt Enable/Disable - used to enable or
disable interrupts
 Supervisor - indicates whether the CPU is executing
in supervisor or user mode.

13
 Control and Status Registers
Program Counter (PC): holds the address of the instruction to
be fetched.
Instruction Register (IR): holds the last instruction fetched.
Memory Address Register (MAR): holds the address of a
memory location that is to be read or written.
Memory Buffer Register (MBR): holds the data to be written to
memory or the data most recently read.
Program Status Word (PSW): Condition Code Flags + other bits
defining the status of the CPU (interrupt enabled/ disabled,
supervisor, etc.)
14
 Some Trade-offs
A large number of general purpose registers→large
number of bits for encoding register operands;
specialization of registers reduces this need.
Too small number of registers creates problems to the
programmer and leads to an increased memory traffic.
The number of general-purpose or data registers is often
between 8 - 32.

15
 Memory Access Registers
Two registers are essential in memory write and read
operations: the memory buffer register (MBR) and
memory address register (MAR).
The MBR and MAR are used exclusively by the CPU and
are not directly accessible to programmers.

16
 Memory Access Registers cont…
In order to perform a write operation into a specified
memory location, the MBR and MAR are used as follows:
1. The word to be stored into the memory location is
first loaded by the CPU into MBR.
2. The address of the location into which the word
is to be stored is loaded by the CPU into a MAR.
3. A write signal is issued by the CPU.

17
 Memory Access Registers cont…
Similarly, to perform a memory read operation, the
MBR and MAR are used as follows:
1. The address of the location from which the word
is to be read is loaded into the MAR.
2. A read signal is issued by the CPU.
3.The required word will be loaded by the
memory into the MBR ready for use by the CPU.

18
 Instruction Fetching Registers
Two main registers are involved in fetching an
instruction for execution: the program counter (PC) and
the instruction register (IR).
The PC is the register that contains the address of the
next instruction to be fetched.
The fetched instruction is loaded in the IR for execution.
After a successful instruction fetch, the PC is updated to
point to the next instruction to be executed.

19
 Example Microprocessor Register Organization

20
 INSTRUCTION CYCLE
Generally CPU must:
 Fetch instructions
 Interpret instructions
 Fetch data
 Write data

21
 Fetch execute cycle

Instruction Fetch

Instruction Decode

Operand Fetch

Execute

Result Store

Next Instruction

22
 Fetch cycle data flow
• During the fetch cycle an instruction is read from the
memory.
• PC contains address of next instruction to be fetched
• This address is moved to MAR and placed on address
bus
• Control unit requests a memory read
• Result is placed on data bus and copied into MBR
and then moved to IR.
• Meanwhile, PC is incremented
23
 Data Flow (Fetch Diagram)

24
 The execute cycle, data flow
• Not simple and predictable, like other cycles
• Takes many forms, since form depends on which of the
various machine instructions is in the IR
• May involve
 transferring data among registers
 read or write from memory or I/O
 invocation of the ALU

25
 Execution Of Instruction

Consider the instruction

Add (R3), R1
which adds the contents of a memory location pointed to by R3
to register R1.
Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand (the contents of the memory location
pointed to by R3).
3) Perform the addition.
4) Load the result into Rl.

26
 DATAPATH
The CPU can be divided into a data section and a control section.
The data section, which is also called the datapath, contains the
registers and the ALU.
The datapath is capable of performing certain operations on data
items.
The control section is basically the control unit, which issues
control signals to the datapath.
Internal to the CPU, data move from one register to another
and between ALU and registers.

27
 DATAPATH cont…
Internal data movements are performed via local buses,
which may carry data, instructions, and addresses.
Externally, data move from registers to memory and I/O
devices, often by means of a system bus.
Internal data movement among registers and between
the ALU and registers may be carried out using different
organizations including one-bus, two-bus, or three-bus
organizations.

28
 One-Bus Organization
Using one bus, the CPU registers and the ALU use a single bus to move
outgoing and incoming data.
Since a bus can handle only a single data movement within one clock
cycle, two-operand operations will need two cycles to fetch the
operands for the ALU.
Additional registers may also be needed to buffer data for the ALU.
This bus organization is the simplest and least expensive, but it limits
the amount of data transfer that can be done in the same clock cycle,
which will slow down the overall performance.

29
 One-bus datapath

30
 Two-Bus Organization
Using two buses is a faster solution than the one-bus
organization.
In this case, general- purpose registers are connected to both
buses.
Data can be transferred from two different registers to the input
point of the ALU at the same time.
Therefore, a two operand operation can fetch both operands in
the same clock cycle.
An additional buffer register may be needed to hold the output of
the ALU when the two buses are busy carrying the two operands.
31
 Two-Bus Organization….

32
 Three-Bus Organization
In a three-bus organization, two buses may be used as source buses
while the third is used as destination.
The source buses move data out of registers (out-bus), and the
destination bus may move data into a register (in-bus).
Each of the two out-buses is connected to an ALU input point.
The output of the ALU is connected directly to the in-bus.
As can be expected, the more buses we have, the more data we can
move within a single clock cycle.
However, increasing the number of buses will also increase the
complexity of the hardware.

33
 Three-bus datapath…

34
 CONTROL UNIT
The control unit is the main component that directs the
system operations by sending control signals to the
datapath.
 These signals control the flow of data within the CPU and
between the CPU and external units such as memory and I/O.
 Control buses generally carry signals between the control unit
and other computer components in a clock-driven manner.
 The system clock produces a continuous sequence of pulses in
a specified duration and frequency.

35
 Control unit cont…
 For each instruction, the control unit causes the CPU to execute a sequence
of steps correctly.
 In reality, there must be control signals to assert lines on various digital
components to make things happen.
 For example, when we perform an Add instruction in assembly language, we
assume the addition takes place because the control signals for the ALU are
set to "add" and the result is put into the AC.
 The ALU has various control lines that determine which operation to
perform.
 The question we need to answer is, "How do these control lines actually
become asserted?"

36
 Control unit cont…
There are two radically different approaches to the design of the
control unit.
The first, is to make the control unit itself a computer within a
computer, and turn each machine instruction into a sequence of
even more primitive instructions called microinstructions.
The alternative approach is to ask what sequence of logical and
arithmetic operations are needed to carry out an instruction, and
then to design the appropriate logic circuit to bring this about.

37
 Control unit cont…
 There are mainly two different types of control units:
1. microprogrammed
2. hardwired.
In microprogrammed control, the control signals associated with
operations are stored in special memory units inaccessible by the
programmer as control words.
In hardwired control, fixed logic circuits that correspond directly
to the Boolean expressions are used to generate the control
signals.

38
 Hardwired control unit
Hardwired control units are implemented through use of
combinational logic units, featuring a finite number of gates that
can generate specific results based on the instructions that were
used to invoke those responses.
The logic circuits can be gates, flip-flops, decoders etc.
The instructions are divided up into fields, and different bits in
the instruction are combined through various digital logic
components to drive the control lines.
Sequence of operations carried out by this machine is determined
by wiring of logic circuits, hence the name “hardwired”.
39
 Hardwired control unit cont…

40
 Hardwired control unit cont…
The key inputs are the instruction register, the clock, flags, and control
bus signals.
In the case of the flags and control bus signals, each individual bit
typically has some meaning (e.g., overflow).
The control unit makes use of the opcode and will perform different
actions for different instructions.
To simplify the control unit logic, there should be a unique logic input
for each opcode.
This function can be performed by a decoder, which takes an encoded
input and produces a single output.
In general, a decoder will have n binary inputs and binary outputs.

41
 Hardwired control unit cont…
We need a special digital circuit that uses , as inputs, the
bits from the Opcode field in our instructions, bits from
the flag (or status) register, signals from the bus, and
signals from the clock.
It should produce, as outputs, the control signals to drive
the various components in the computer.

42
 Hardwired control unit cont…
Advantage:
 Can operate at high speed.
Disadvantages:
 instruction set and the control logic are directly tied together
by special circuits that are complex and difficult to design or
modify.(If someone designs a hardwired computer and later
decides to extend the instruction set, the physical components
in the computer must be changed.
 This is prohibitively expensive, because not only must new
chips be fabricated but also the old ones must be located and
replaced.
43
 Microprogrammed control unit
A control unit whose binary control variables are stored in memory is
called a microprogrammed control unit.
The control variables at any given time can be represented by a string
of 1's and 0's called a control word.
Each word in control memory contains within it a microinstruction.
The microinstruction specifies one or more microoperations for the
system.
A sequence of microinstructions constitutes a microprogram.
A memory that is part of a control unit is referred to as a control
memory.

44
 Microprogrammed control unit

45
 Microprogrammed control unit cont…
The control memory is assumed to be a ROM, within which all
control information is permanently stored.
The control memory address register specifies the address of the
microinstruction and the control data register holds the
microinstruction read from memory: the microinstruction contains a
control word that specifies one or more microoperations for data
processor.
The next address generator is sometimes called a microprogram
sequencer, as it determines the address sequence that is read from
control memory, the address of the next microinstruction can be
specified several ways, depending on the sequencer inputs.
46
 Microprogrammed control unit cont…
Typical functions of a microprogram sequencer are
 incrementing the control address register by one,
 loading into the control address register an address from
control memory,
 transferring an external address or loading an initial
address to start the control operations.

47
 Microprogrammed control unit cont…
Advantages
 It simplifies the design of control unit. Thus it is both, cheaper
and less error prone implement.
 Control functions are implemented in software rather than
hardware.
 The design process is orderly and systematic.
 More flexible, can be changed to accommodate new system
specifications or to correct the design errors quickly and
cheaply.
 Complex function such as floating point arithmetic can be
realized efficiently.
48
 Microprogrammed control unit cont…
Disadvantages
 A microprogrammed control unit is somewhat slower
than the hardwired control unit, because time is
required to access the microinstructions from CM.
 The flexibility is achieved at some extra hardware cost
due to the control memory and its access circuitry.

49