Introduction to Microprocessor T. H. M.

Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

 What is Microprocessor?

The integrated Circuit (IC) chip containing the CPU is called the microprocessor
and the entire computer including the microprocessor, memory and I/O is called a
microcomputer.

32-bit vs. 64-bit CPU

 The terms 32-bit and 64-bit refer to the way a computer's processor (also
called a CPU), handles information. The 64-bit version of Windows handles large
amounts of random access memory (RAM) more effectively than a 32-bit system
 A 64-bit processor is capable of storing more computational values, including
memory addresses, which means it’s able to access over four billion times as
much physical memory than a 32-bit processor.

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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

 General Architecture of microcomputer.

There are three major parts of a Computer System.

1. Central Processing Unit (CPU): Also simply called as the microprocessor
and acts as the brain coordinating all activities within a computer.
Executes (processes) the information stored in memory.
2. The Memory: The program instructions and data are primarily stored
(RAM, ROM).
3. The Input/output (I/O) Devices: Allow the computer to input
information for processing and then output the results. I/O Devices are
also known as computer peripherals.
Input unit: keyboard, mouse, scanner, etc.
Output unit: Monitor printer, etc.

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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

The CPU is connected to memory and I/O devices through a strip of

wires called a bus. The bus inside a computer carries information from
place to place. In every computer there are three types of busses:
 Address Bus
 Data Bus
 Control Bus

Address Bus:
 The 8086 CPU is has 20-bit address bus, where the AD0-AD15
and A16-A20 are used as the address bus.
 To demultiplex the address signals from the address/data pins
(AD0-AD15) a latch must be used to grab the addresses.
 The most widely used latch for demultiplexing is 74LS373 IC.
 For 8088 the address bus is 20 bit and data bus is 8-bit. So only
8-bit is latched

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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

Data Bus:
 In 8086 CPU Pins AD0 – AD15 are used for the data bus.
 The ALE (Address Latch Enable –pin 25) signals whether the information
on pins AD0 –AD15 is used address or data.
 When ALE is low indicates that AD0-AD15 will be used as data bus
 When ALE is high indicating that AD0-AD15 will be used as address bus

Control Bus: is used to indicate

 When a valid address is on the address bus

 In which direction data are to be transferred over the data bus (in/out)
 When external devices can read/write data on the data bus.
 When valid read/write data are on the data bus.
 etc

 The address and control bus contains output lines only, therefore it is
unidirectional, but the data bus is bidirectional.
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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

 General Architecture of microcomputer.

Fig: Internal organization of a microcomputer.

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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

Inside the CPU?

A program stored in the memory provides instructions to the CPU to
perform a specific action. This action can be a simple addition. It is
function of the CPU to fetch the program instructions from the memory
and execute them
1. The CPU contains a number of registers to store information inside the CPU
temporarily. Registers inside the CPU can be 8-bit, 16-bit, 32-bit or even 64-bit
depending on the CPU.

2. The CPU also contains Arithmetic and Logic Unit (ALU). The ALU performs
arithmetic (add, subtract, multiply, divide) and logic (AND, OR, NOT) functions.

3. The CPU contains a program counter also known as the Instruction Pointer to point
the address of the next instruction to be executed.

4. Instruction Decoder is a kind of dictionary which is used to interpret the meaning

of the instruction fetched into the CPU. Appropriate control signals are generated
according to the meaning of the instruction.
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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

Brief History of the Computers and Evolution of

Intel 80 X 86 family μ processor
1946 The first generation of Computer ENIAC was started to be used
based on the vacuum tube technology.
1958 the first transistorized computer TRADIC was announced by IBM.
1959 first IC was invented.
1960s ICs were started to be used in CPU boards.
1970s entire CPU was put in a single chip. (1971 the first
microprocessor of Intel 4004 (4-bit data bus and 2300 transistors)
Late 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit
address bus and used from traffic light controllers to homemade
computers.
1981 First PC was introduced by IBM with Intel 8088 microprocessor.

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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

Evolution from 8080/8085 to 8086

 Intel introduced 8086 microprocessor in 1978. This 16-bit
microprocessor was a major improvement over the previous generation
of 8080/8085 series of microprocessors.
8086 8080/8085

1 megabyte Memory of 64 kilobyte

(20-bit add. bus) (16-bit add. bus)

16-bit Data bus 8-bit data bus

Pipelined processor
Non-pipelined μpr
(first single-chip μpr.)

 In a system with pipelining, the data and the address bus are busy
transferring data while the CPU is processing information.

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 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

Other microprocessors
 80286: Intel introduced 80286 in 1982.
 With 16-bit internal and external data bus.
 24-bit address bus (224 = 16 megabyte)
 Virtual memory. a way of fooling the microprocessor into thinking
that it has access to unlimited memory by swapping data between disk
storage and RAM.
 Real mode (faster operation with maximum of 1 Mbytes of memory)
vs. protected mode protecting the operating system for accidental or
deliberate destruction of the user. Protected mode is slower but can
use 16 Mbytes of memory.
 80386: introduced in 1985 also known as (80386DX)
 With 32-bit internal and external data bus.
 32-bit address bus (232 = 4 gigabyte-physical memory). With virtual
memory 64 terabytes (246).
 80386SX was later introduced with the same internal structure with
16-bit external data bus and 24-bit address bus. 80386SX was much
cheaper. 9
 Introduction to Microprocessor T. H. M. Sumon Rashid
Lecture-1 Asst. Prof., EEE, PUST

Other microprocessors
All microprocessors discussed so far were general-purpose
microprocessors and could not handle mathematical operations rapidly. For
this reason, 8087, 80287, 80387 numeric data processing chips called
math co-processors were used.

 80486: introduced in 1989 with 32-bit internal-external data bus

and 32-bit address bus.
 Built in math co-processor in a single chip.
 Introduction of cache memory ( Static RAM with very fast
access time)

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-1 (CONT……)

 RISC AND CISC PROCESSOR

 Multiplying two Numbers in Memory

 The CISC Approach

MULT 2:3, 5:2

 The RISC Approach

LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-1 (CONT……)

 The Performance Equation

Equation commonly used for expressing a computer's performance ability:
𝐓𝐢𝐦𝐞 𝐓𝐢𝐦𝐞 𝐜𝐲𝐜𝐥𝐞𝐬 𝐢𝐧𝐬𝐭𝐫𝐮𝐜𝐭𝐢𝐨𝐧𝐬
= 𝐱 𝐱
𝐩𝐫𝐨𝐠𝐫𝐚𝐦 𝐜𝐲𝐜𝐥𝐞 𝐢𝐧𝐬𝐭𝐫𝐮𝐜𝐭𝐢𝐨𝐧 𝐩𝐫𝐨𝐠𝐫𝐚𝐦

CISC Vs. RISC APPROACH

CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock complex instructions Single-clock, reduced instruction only

Memory-to-memory: "LOAD" and "STORE" Register to register: "LOAD" and "STORE"

incorporated in instructions are independent instructions

Small code sizes, high cycles per second Low cycles per second, large code sizes

Transistors used for storing complex instructions Spends more transistors on memory registers

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-1 (CONT…)

 Some Types of Microprocessors:

Type Year Transistors Clock Rate Data bus Add. Bus Memory size
Intro. (MHz.) EXT. INT. Bus

Intel family:
4004 1971 2,250 0.108 4 8 12
8008 1972 3,500 0.200 8 8 14
8080 1974 6,000 3 8 8 16
8085 1976 6,000 6 8 8 16
8086 1978 29,000 10 16 16 20 1M
8088 1979 29,000 10 8 16 20 1M
80286 1982 134,000 12.5 16 16 24 16M
80386DX 1985 275,000 33 32 32 32 4G
80486SX 1988 275,000 33 16 32 24 16M
Pentium C 1993 3,100,000 66 -200 64 32 32
Pentium-Pro 1995 5,500,000 200 64 32 36

Pentium-III 1999 9,500,000 550-733 64 32 36

Motorola family:

6800 8 64K

68060 64 4G + 16K cache

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-1 (CONT…)

Some important terminology

bit 0
nibble 0000
byte 0000 0000
word 0000 0000 0000 0000
double-word 0000 0000 0000 0000 0000 0000 0000 0000
quad-word 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

1 kilobyte is 210 bytes. (Abbreviation K is used) Some floppy disks hold 356K bytes of
data.
1 megabyte is 220 bytes. (a little over a million 1,048,576)
1 gigabyte is 230 bytes (over 1 trillion)
1 terabyte is 240 bytes

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2

 Internal Architecture of the 8086/8088

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

Microprocessors have two major components

The Execution unit (EU)
The Bus interface unit (BIU)
Execution unit:
 mainly to execute instructions.
 it contains a circuit called the arithmetic and logic unit (ALU).
 ALU performs arithmetic (+, - , *, /) and logic (AND, OR, NOT) operations.
 the data for operations are stored in circuit called Registers.
 it has eight registers for storing data (AX, BX, CX, DX, SI, DI, BP, and SP), status and
control flags and temporary-operand registers.

Bus interface unit (BIU):

 facilitates communication between the EU and memory or I/O circuits.
 It is responsible for transmitting address, data, and control signals on the buses.
 This bus includes 16-bit bidirectional data bus, a 20-bit address bus, and the signals
needed to control transfer over the bus.
 Its registers are named CS, DS, ES, SS, IP; they hold addresses of memory locations.
 The IP contains the address of next instruction to be executed by the EU
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

 Pipelining

Pipelined vs. Non-pipelined Execution

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

 Pipelining
 Intel implemented the concept of pipelining by splitting the internal structure of 8088/86
into two sections.
 the execution unit (EU)
 the bus interface unit (BIU)
 These two sections work simultaneously. BIU accesses memory and peripherals while the
EU executes the instructions previously fetched.
 It only works if BIU keeps ahead of EU. Thus BIU has a buffer of queue. (8088 has 4
byte, and 8088 has 6 bytes).
 If the execution of any instruction takes to long, the BIU is filled to its maximum capacity
and busses will stay idle. It starts to fetch again whenever there is 2-byte room in the
queue.
 Branch Penalty
 When there is a jump instruction, the microprocessor must flush out the queue. When a jump
instruction is executed BIU starts to fetch information from the new location in the memory.
In this situation EU must wait until the BIU starts to fetch the new instruction. This is known
as branch penalty.
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

 8086/8088 Pin Diagram

Fig: Pin diagram of 8086 and 8088 Microprocessor.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

READY: READY is the acknowledgement from the addressed memory or I/O device that it will
complete the data transfer.

INTR: Interrupt request is used to request a hardware interrupt. If INTR is held high when IF=1,
the 8086/8088 enters an interrupt acknowledge cycle (INTA become active) after the current
instruction has completed execution.

NMI: The Non-maskable Interrupt input similar to INTR except that the NMI interrupt does not
check to see if the IF flag bit is logic 1.

BHE/S7: The bus high enable pin is used to enable the most significant data bus bits (D15-D8)
during a read or write operation.

TEST: This input pin is examined by a ‘WAIT’ instruction. If TEST is logic 0, the WAIT
Instruction functions as NOP. If TEST is logic 1 then the WAIT instruction waits for TEST to
become logic 0. This pin is most often connected to the 8087 numeric co-processor.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

HOLD: Active-high input from the DMA controller which indicates that the device is requesting
access to memory and I/O space and that the CPU should release the control of the local bus.

HLDA: Active-high output signal. After input on HOLD, the CPU responds with HLDA to
signal that DMA (Direct Memory Access) controller can use the bus.

Direct Memory Access (DMA):

In computers there is often need to transfer a large amount of data between the
memory and peripherals such as hard disk. In such a case using the CPU to transfer
data is too slow, since the data first must be fetched into the CPU and then sent to its
destination.

For this reason Direct Memory Access controller is used to bypass the CPU and
provide a direct connection between the peripherals and memory, thus transferring the
data as fast as possible.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

MN Vs MX
Minimum mode:

 Operated in minimum mode by strapping its MN/MX pin to logic 1.

 The 8086 processor works in a single processor environment.
 All control signals for memory and I/O are generated by the microprocessor.

Maximum mode:
 operated by strapping the MN/MX pin
to ground
 processor derives the status signal S2,
S1, S0.
 Another chip called bus controller
derives the control signal using this
status information.
 It is designed to be used when a
coprocessor exists in the system.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-2 (CONT…)

Basic Busses for a computer:

The 3 control signals from 8088: WR, RD, and IO/M are used to generate 4 new
control signals (MEMR, MEMW, IOR, and IOW)by using a decoder circuit.

Fig. 8088 Address Buss, Data Bus and Control Buses

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3

 Registers of 8086
 In the CPU, registers are used store information temporarily. The information can be one
or two bytes of data, or the address of data.
 In 8088/8086 general-purpose registers can be accessed as either16-bit or 8-bit registers.
All other registers can be accessed as full 16-bit registers.
AX
16-bit register

AH AL
8-bit reg. 8-bit reg.

 The bits of the registers are numbered in descending order.

8-bit register:
D7 D6 D5 D4 D3 D2 D1 D0

 Different registers are used for different functions. Registers will be explained later
within the context of instructions and their applications.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3

 The first letter of each general register indicates its use.

 AX is used for the accumulator.
 BX is used for base addressing register.
 CX is used for counter loop operations.
 DX is used to point out data in I/O operations

Category Bits Register Names

General 16 AX, BX, CX, DX
8 AH, AL, BH, BL, CH, CL, DH, DL
Pointer 16 SP (stack pointer), BP(base pointer)
Index 16 SI (source index), DI(destination index)
Segment 16 CS (code segment), DS(data segment)
SS (stack segment), ES(extra segment)
Instruction 16 IP (instruction pointer)
Flag 16 FR (flag register)

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3 (CONT…)

Instruction pointer (IP):

 16 bits in length and identifies the location of the next word of instruction
code to be fetched from the current code segment of memory,
 it contains the offset of the next word of instruction code instead of its
actual address.
Data Registers:
 four general-purpose data register (AX,BX,CX and DX)
 can be used as the source or destination operand
 Can be accessed as 16 bits or as two 8-bits registers
Pointer and Index Registers:
 two pointer registers SP and BP, and two index registers DI and SI.
 SS and BP are used with SS to access memory location within the stack
segment.
 SI and DI are used with DS or ES to generate addresses for instructions that
access data stored in the data segment of memory.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3 (CONT…)

Flag Register: There are two types of flags:

 Status/Conditional flags: which reflect the result of executing an

instruction. The programmer cannot set/reset these flags directly. The
status register also called flag register: is 16-bit register with only
nine bits that are implemented (see Fig ). Six of these are status flags:
CF, PF, AF, ZF, SF, and OF

 Control flags: enable or disable certain CPU operations. The programmer

can set/reset these bits to control the CPU's operation. There are 3 control
flags: TF, IF and DF.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3 (CONT…)

 PROGRAM SEGMENTS

 A segment is an area of memory that includes up to 64K bytes and begins an

address evenly divisible by 16 (such an address ends in 0H).
 Assembly Language Program consists of three segments:
 code segment : contains the program code (instructions)
 data segment : used to store data (information) to be processed by the
program
 stack segment: used to store information temporarily.

Logical Vs Physical Address

Physical Address: is the 20-bit address that actually put on the address bus. (in
8086)
• Has a range of 00000H - FFFFFH

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3 (CONT…)

Logical address: is described by combining two parts: Segment address and offset
address.
Segment address is 16-bit data from one of the segment registers (CS, SS, DS
and ES).
Offset address is 16-bit data from one of the index and pointer registers (DI,
SI, SP and BP). Also it could be base register BX. It is a location within 64K
byte segment range. Has a range of 0000H – FFFFH.
To express the 20-bit Physical Address of memory
 Multiply Segment register by 10H ( or shift it to left by four bit)
 Add it to the offset

Example1: if CS = 002AH, and IP = 0023H, write the logical address that they
represent, then map it to Physical address.
Solution:
Logical address = CS: IP
002A: 0023
Physical address = (CS X 10H) + IP = 002A0 +0023 = 002C3 29
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-3 (CONT…)

 Generating a memory address

Offset value:
IP
BP
DI
SI
or BX

Segment
Register:
CS
SS
DS

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-4

 Addressing Modes of 8086

An instruction acts on any number of operands. The way an instruction accesses its
operands is called its Addressing modes.
Operands may be of three types:
Implicit
XLAT; automatically takes AL and BX as operands
Explicit
MOV AX, BX; it takes AX and BX as operands
Both Implicit and Explicit
MUL BX; automatically multiply BX explicitly times AX

We can classify the addressing modes of 8086 into four groups:

Immediate addressing
Register addressing
Memory addressing
I/O port addressing
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-4

Immediate Addressing: Example:

 source operand is a constant MOV BX,1234H ; move 1234H into BX
ADD AX, 5 ; AX = AX+5
 resides in the code segment MOV DS,1234H ;illegal
 faster to execute an instruction
 possible in all registers except segment and flag
registers.

Register addressing Example:

 no need to compute the effective MOV AX, BX
address ADD AX, SI
 no memory access involved

Note: we can’t use CS as the destination operand.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-4

Memory addressing
Memory (RAM) is the main component of a computer to store temporary data and
machine instructions.
There are different forms of memory addressing modes:

 Direct Addressing:  Register indirect addressing

mov al,ds:[8088h]
mov al, [bp]

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-4 (CONT…)

 Based indexed addressing:  Based indexed displacement addressing:

 The combination of the based and indexed

addressing modes.
 One base register and one index register are mov al, disp[bx+di]
used.

mov al, [bx+si]

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-4 (CONT…)

4. Based indexed with displacement:

MOV AL, [BX + SI +100H]

Offset Registers for various Segments

Segment register CS DS ES SS
Offset register (s) IP SI, DI, BX SI,DI, BX SP, BP
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-4 (CONT…)

8086 Pentium Pro Data addressing Modes:

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-5
INTRODUCTION TO ASSEMBLY LANGUAGE PROGRAMING

 Instruction Set of 8086

Various types of Instructions are -
1. Data transfer instructions
2. Arithmetic instructions
3. Logic instructions
4. Shift instructions
5. Rotate instructions

1. Data transfer instructions

Data Transfer between CPU and the
Memory Example:
 MOV
MOV BYTEPTR ds : [SI], 37H
MOV al, BYTEPTR ds : [SI]
MOV destination, source
MOV ax, WORDPTR ds : [SI]
MOV CX, 037AH ; MOV 037AH into the CX.
MOV AX, BX ; Copy the contents of register BX to AX
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-5

 MEMORY MAP OF THE IBM PC

 The 20-bit address of the 8086/8088 allows 1M byte of (1024 K
bytes) memory space with the address range 00000-FFFFF.
 The allocation of the memory is called a memory map.
RAM:
 Memory locations from 00000H to 9FFFFH (640K) are
set aside for RAM.
 In an IBM PC the DOS operating system first allocates
the available RAM on the PC for its own use and let the
rest be used for applications such as word processors.
Video RAM:
 Memory locations from A0000H to BFFFFH (128K) are set aside for video.
 Amount varies depending on the video board installed on the PC.
ROM:
 Memory locations from C0000H to FFFFFH (256K) are set aside for ROM.
 First 64 K bytes is used by BIOS (Basic Input/Output System) ROM
 Some of the remaining space is used for adapter cards.
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-5
Stack:
 a section of read/write memory (RAM)
 Used by CPU to store data and address temporarily
 stack is 64Kbytes long
 SS (stack segment) and SP (stack pointer) must be loaded to access stack in
the memory.
 Every register in the CPU (except segment registers and SP) can be stored in
the stack and loaded from the stack.
 PUSH: Storing the CPU register in the stack is called a PUSH.
PUSH Source

Example: SP=1236, AX=24B6, DI=85C2, and

DX=5F93, show the contents of the stack as each
instruction is executed.
PUSH AX
PUSH DI
PUSH DX

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-5 (CONT…)

 POP: Loading the contents of the stack into the CPU register is called a POP.
POP destination
Example: assume that the stack is shown below, and
SP=18FA, show the contents of the stack and
registers as each of the following instructions is
executed.
POP CX
POP DX
POP BX

 XCHG
XCHG destination, source

Example: For the figure below. What is the result of

executing the following instruction?

XCHG AX, [0002]

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-5 (CONT…)

 XLAT
XLAT
A XLAT instruction first adds AL to BX to form a memory address in
data segment. It then copies the contents of this address to AL.

Example: For the figure below, what is the result of executing the following instruction?

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-5 (CONT…)

 LEA: Example 3: For the figure below, what is the

LEA register, source result of executing the following instruction?
SI= DI + BX + 2H = LEA SI , [ DI + BX + 2H]
0062H

 IN
IN accumulator, port

IN AL, 0C8H; Input a byte from port

0C8H to AL
 LDS:
LDS register, memory address
LDS SI, [DI  OUT
+ BX + 2H] OUT port, accumulator AL or AX

OUT 3BH, AL; Copy the contents of the AL

to port 3B

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SI= DI+ BX +
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-6

Example: For the figure below,

2. Arithmetic Instructions
 What is the result of executing the following
instruction?
ADD  What is the addressing mode for this instruction?
ADD destination, source  What is the PA is BP register used instead of BX
register?
ADD AX, [DI + BX + 2H]

ADC: Add with carry EA= [DI + BX + 2H] =[0020 + 0040 + 02H ]= 0062H
Example: let num1=11223344H and num2=55667788H are PA = (DS × 10H) + EA = 1000H +0062H= 1062H
stored at memory locations 200 and 300 respectively in the Memory word stored at location 1062H is 9067
current data segment. ADD num1and num2 and store the AX = AX + 9067
result at memory location 400.
11223344H
55667788H

MOV AX, [0200]

MOV BX, [0202]
ADD AX, [0300]
ADC BX, [0302]
MOV [0400], AX
MOV [0402], BX

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-6 (CONT…)

INC Example: For the figure below, what is the

INC destination result of executing the following instructions?
;AX = 7FFFh
INC AX ; After this instruction INC WORD PTR [0040]
AX = 8000h INC BYTE PTR [0042]

MUL
MUL source

; AL = 21h (33 decimal), BL = A1h (161 decimal)

MUL BL ; AX =14C1h (5313 decimal)

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-6 (CONT…)

DIV
Div source

Example: Assume that each instruction starts from these values:

AL = 85H, BL = 35H, AH = 0H
MUL BL; =AL. BL = 85H * 35H = 1B89H →AX = 1B89H
IMUL BL; =AL. BL= 2’SAL * BL= 2’S (85H) * 35H
=7BH * 35H = 1977H→2’s comp→E689H →AX.
AH (remainder) AL (quotient)
DIV BL
1B 02

AH (remainder) AL (quotient)

IDIV BL 1B 02

45
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-7

3. LOGICAL INSTRUCTIONS
AND
NOT
NOT destination
AND op1, op2

 perform the bitwise complement of  Performs a bitwise Logical AND of

operand two operands
 stores the result back into operand  Used to clear certain bits in the
itself. operand (masking).

NOT BX AND BH, CL

OR xxxx xxxx
OR destination, source. 0000 0111
(OR)
Example: set the lower three bits of BL register
OR BL, 07H xxxx x111

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-7

XOR
XOR destination, source.

 Used to invert certain bits (toggling bits)

 Used to clear a register by XORed it with itself

Example:
XOR BX, CX ; Exclusive OR CX with BX and Result in BX
BX = 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 1
CX = 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
------------------------------------- --------------
BX = 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 0

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-7

3. LOGICAL INSTRUCTIONS

TEST
TEST operand1, operand2

The TEST instruction works same as the AND operation, but

unlike AND instruction, it does not change the first operand. So,
if we need to check whether a number in a register is even or
odd, we can also do this using the TEST instruction without
changing the original number.

Example: TEST AL, 01H

JZ EVEN_NUMBER

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-7 (CONT…)

SHL
SHL destination, source

;shift left

SHL AX,1

SHR

; Shift Right

;DX=1234H
MOV CL, 2H
SHR DX, CL 49
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-8

ROL
ROL destination, count Example:
MOV AL, 47H ; AL=0100 0111
ROL AL, 1 ; AL=1000 1110 CF=0
ROL AL,1 ; AL=0001 1101 CF=1
ROL AL,1 ; AL=0011 1010 CF=0
ROL AL,1 ; AL=0111 0100 CF=0

RCL
RCL destination, count Example:
;rotate left through carry STC ;set carry, make CF=1
MOV BL,15H ;BL=0001 0101 CF=1
RCL BL,1 ;BL=0010 1011 CF=0
RCL BL,1 ;BL=0101 0110 CF=0

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-8 (CONT…)

ROR RCR
; rotate right ;rotate right through carry

Example:
Example: STC ; set carry, make CF=1
MOV BX, C7E5H ; BX=1100 0111 1110 0101 MOV BX, 37F1H ; BX=0011 0111 1111 0001 CF=1
MOV CL, 6 ; CL=6 number of times to rotate MOV CL=5 ;CL=5 number of times to rotate
ROR BX, CL ; BX=1001 0111 0001 1111 CF=1 RCR BX, CL ;BX=0001 1001 1011 1111 CF=1

CMP Flag settings of the CMP instruction.

CMP dest, source
Compare operands CF ZF

Example:
Destination >source 0 0
MOV AL, 5
MOV BL, 5 Destination = source 0 1
CMP AL, BL Destination < source 1 0
RET

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-8 (CONT…)

Flag Control Instruction

A group of instructions that directly affect the state of the flags:

Example: Write an instruction sequence to save the current contents of the 8086’s
flags in the memory location pointed to by SI and then reload the flags with the
contents of memory location pointed to by DI.
Solution:
LAHF
MOV [SI], AH
MOV AH, [DI]
SAHF 52
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-8 (CONT…)
GENERAL RULES FOR 8086/8088 INSTRUCTIONS
1. An immediate value (i.e., a constant) cannot be a destination operand.
For example, the following is invalid: ADD 34BFh, BX
2. The destination and source operands must be of the same size, except if the source operand is an
immediate value of a lower size than the destination.
For example, the following is valid: MOV AX, 03H
3. Direct memory to memory transfer is invalid, except for string instructions. Such a transfer must
be done indirectly using a general register of the appropriate size.
For example, if VAR1 and VAR2 are word variables (i.e., word memory operands) then the transfer:
MOV VAR1, VAR2 is invalid. The transfer can be done as:
MOV AX, VAR2
MOV VAR1 , AX
4. The transfer MOV SegmentRegister , SegmentRegister is invalid for all segment registers:
CS, DS, SS, ES.
5. The transfer: MOV SegmentRegister , ImmediateValue is invalid for all Segment
Registers: CS, DS, SS, ES. Such a transfer can be done indirectly using a 16-bit general register.
For example, if a program has a data segment that is defined by a simplified segment
directive .DATA, the DS register can be initialized by:
MOV BX, @DATA
MOV DS, BX
6. The IP, CS, SS, and SP registers cannot be destination operands.
For example, the following is invalid: MOV CS, 2345H 53
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9

 Program execution transfer instructions

Jump Instructions
JMP
JMP Operand

JMP 1234H
conditional unconditional JMP BX

Conditional Jump
 control is transferred to a new location if a certain condition is met.
JC Jump if carry flag CF = 1[CF is checked]
JNZ Jump if not zero (ZF = 0) [ZF is checked]
Unconditional Jump types:
“JMP label” is the unconditional jump in which control is transferred unconditionally
to the target label. Unconditional jump can take the following forms.
a) Intrasegment: Only IP is changed.
i) Short Jump: JMP short Label (8 bit)
54
ii) Near Jump: JMP near Label (16 bit)
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9

b) Intersegment: Both CS and IP are changed.

Short Jumps:
 All conditional jumps are short jumps. In a short jump the address of the target
must be within –128 to +127 bytes of the memory.
 A conditional jump is a two-byte instruction: one byte is the opcode of the J
condition and the second value is a value between 00 to FF.
 In a backward jump the second byte is the 2’s complement of the displacement
value.
Note: Two's complement is executed by
1) inverting (i.e. flipping) all bits, then
2) adding a place value of 1 to the inverted
number.
NEAR Jump:
It is exactly same as the short jump, except that the target address can be
anywhere within the range of +32767 to –32768.
FAR Jump:
FAR JUMP, has the format “JMP FAR PTR label”. This is the jump out of the
current code segment, meaning that not only the IP, but also the CS is replaced
with new values. 55
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9

 Conditional Jumps

56
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9 (CONT…)

Example: Write a program to add (50)H numbers stored at memory

locations start at 4400:0100H, then store the result at address
200H in the same data segment.

MOV AX, 4400H

MOV DS, AX
MOV CX, 0050H counter
MOV BX, 0100H offset
Again: ADD AL, [BX]
label
DEC CX
JNZ Again
MOV [0200], AL

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9 (CONT…)

Example: Write a program to move a block of 100 consecutive bytes

of data starting at offset address 400H in memory to another block
of memory locations starting at offset address 600H. Assume both
block at the same data segment F000H.

MOV AX, F000H

MOV DS, AX
MOV SI, 0400H
MOV DI, 0600H
MOV CX, 64H 64 Hexadecimal == 100 Decimal
LableX : MOV AH, [SI]
MOV [DI], AH
INC SI
INC DI
DEC CX
JNZ LableX
HLT End of program

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9 (CONT…)

CALL STATEMENTS

 used to call a procedure/subroutine.

 The target address can be in the current segment, hence a NEAR call (IP is
changed CS is not).
 The target address can be outside the current segment, hence FAR call (IP and
CS are changed)
 To make sure that after the execution of the called subroutine the microprocessor
knows where to come back, the microprocessor automatically saves the address
of the instruction following the call on the stack.
 RET instruction must be included at the end of the subroutine to initiate the
return sequence to the main program environment.
 RET (return) instruction, which directs CPU to pop the address of the next
instruction before the called subroutine to be restored.

Examples: CALL 1234h CALL [BX]

CALL BX CALL DWORD PTR [DI]
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-9 (CONT…)

Example: write a procedure named Square that squares the contents of BL and places
the result in BX.
Solution:
Example: write a program that computes y =
Square: PUSH AX (AL)2 + (AH)2 + (DL)2, places the result in
MOV AL, BL CX. Make use of the SQUARE subroutine
MUL BL defined in the previous example. (Assume
MOV BX, AX result y doesn’t exceed 16 bit)
POP AX
RET MOV CX, 0000H
MOV BL, AL
CALL Square
ADD CX, BX
MOV BL, AH
CALL Square
ADD CX, BX
MOV BL, DL
CALL Square
ADD CX, BX
HLT 60
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Interrupt of 8086

Definition: The meaning of ‘interrupts’ is to break the sequence of

operation. While the cpu is executing a program, on ‘interrupt’ breaks
the normal sequence of execution of instructions, diverts its
execution to some other program called Interrupt Service Routine
(ISR). After executing ISR , the control is transferred back again to
the main program. Interrupt processing is an alternative to polling.

Types of Interrupts: Two types of Interrupts in 8086.

1) Hardware Interrupts: INTR are NMI both are hardware interrupt.

2) Software Interrupts : (Internal Interrupts and Instructions)
Software interrupts can be caused by:
 INT instruction
 INT <interrupt number>

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Interrupt vectors

 The first 1024 bytes of memory (addresses 00000 –003FF) always

contain the interrupt vector table. Always. Never anything else.
 Each of the 256 vectors requires four bytes—two for segment, two
for offset

Memory addresses interrupt numbers

003FC INT 255
4*x INT x
00008 INT 2
00004 INT 1
00000 INT 0

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Need for Interrupt: Interrupts are particularly useful when interfacing I/O
devices that provide or require data at relatively low data transfer rate.

– The INT instruction works like a FAR call. When it is invoked, it saves CS:
IP and the flags on the stack and goes to the subroutine associated with
the interrupt.
INT xx ;the interrupt number can be 00 – FFH (256 possible interrupts)

Example:
INT data8 ; data8 is an interrupt vector from 0 to 255
INT does the following:
– Pushes flag register (PUSHF)
– Pushes return CS and IP
– Far jumps to [0000 :( 4*data8)]
– Usually clears the interrupt flag disabling the interrupt system
IRET is to INT what RET is to CALL
– Pops flag register (POPF)
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– Performs a far return
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Differences between Hardware and software interrupt

Software interrupt Hardware interrupt

I. It is synchronous event. It is asynchronous event.

ii. This interrupt is requested by This interrupt is requested by external

executing interrupt instruction. device.
III. It cannot be ignored or masked. It can be masked.

iv.It has highest priority among all The priority is lower than that of software
interrupts. interrupt.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Programming Languages

Machine Language:
• Programs consist of 0s and 1s are called machine language.
• Assembly Languages provided mnemonics for machine code
instructions.
• Mnemonics refer to codes and abbreviations to make it easier for the
users to remember.

Low / High level languages:

• Assembly Language is a low-level language. Deals directly with the
internal structure of CPU. Assembler translates Assembly language
program into machine code.
• In high-level languages, Pascal, Basic, C; the programmer does not have
to be concerned with internal details of the CPU. Compilers translate
the program into machine code.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Assembly Language programming:

• Assembly Language program consists of series of lines of Assembly language
instructions.
• Instruction consists of a mnemonic and two operands.

BIOS and DOS programming in Assembly

BIOS and DOS contain some very useful subroutines, which can be used through
INT (interrupt) instruction.

BIOS INT 10H PROGRAMMING

 INT 10H subroutines are in the ROM BIOS of the 80x86-based IBM PC.
 Depending on the value put in AH many function associated with the
manipulation of screen text or graphics is performed.
 Among these functions, clearing the screen, changing the cursor position, change
the screen color and drawing lines on the screen

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Monitor screen in text mode

 In normal text mode the screen is divided into 80
columns and 25 rows.
 Top left = 00,00
Bottom left = 24,00 (decimal)
Bottom right = 24,79 (decimal)
Clearing the screen ( INT 10H function 06H)
 AH=06 Scroll window up
 To clear the screen with INT 10H the
following registers must contain certain
values.
AH=06, AL=00, BH=07, CX=0000 DH=24,
DL=79
MOV AX,0600H ;scroll entire screen
MOV BH,07 ;normal attribute
MOV CX,0000 ;start at 00,00
MOV DX,184FH ;end at 24,79 (hex=18,4F)
INT 10H ;invoke the interrupt
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

INT 10H function 02: setting the cursor to a specific location

AH=02 Set cursor position

BH= page number (BH=00) ; 00 represents the current viewed page.
DH = row
DL = column

Example: Write the code to set the cursor position to row = 15 (= 0FH) and column
= 25 (=19H).

MOV AH,02 ;set cursor option

MOV BH,00 ;page 0
MOV DH,15 ;row position
MOV DL,25 ;column position
INT 10H ;invoke interrupt
10H

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

DOS INT 21H PROGRAMMING

 INT 21H subroutines are provided by DOS Operating system.

 Depending on the value put in AH many functions such as inputting data from the
keyboard and displaying it on the screen can be performed.

INT 21H option 07: Keyboard input without echo

 This function waits until a character is input from the keyboard, then character is
not displayed (echoed) to the monitor.
 After the interrupt the character will be in AL.

Example:
MOV AH,07 ;keyboard input without echo
INT 21H ;after the interrupt, AL = input character (ASCII)

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

INT 16H Keyboard Programming:

 In the previous sections it was explained that INT 21H function AH=07, waits for
the user to input a character.
 In some programs a task must run continuously while checking a key press? Such
cases require to use INT 16H.

Checking a key press: AH=01

Ex:
MOV AH,01 ;check for key press
INT 16H ;using INT 16H

After the execution, ZF=0,if there is a key press;

ZF=1 if there is no key press.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Example: Write a program segment to (1) clear the screen and (2) set the cursor at
the center of the screen.
;clearing the screen
MOV AX,0600H ;scroll entire screen
MOV BH,07 ;normal attribute
MOV CX,0000 ;start at 00,00
MOV DX,184FH ;end at 24,79 (hex=18,4F)
INT 10H ;invoke the interrupt

;setting the cursor to the center of the screen

MOV AH,02 ;set cursor option
MOV BH,00 ;page 0
MOV DH,12 ;center row position
MOV DL,39 ;center column position
INT 10H ;invoke interrupt 10H

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10

Example: Write an assembly language program to add 1+2+3+...+10.

mov cx, 10 ; The counter is in CX
mov ax, 0 ; I use AX as a sum holder
myloop:
add ax, cx ; ax = ax + cx
dec cx ; decrement the counter
cmp cx, 0 ; is cx zero?
jne myloop ; if not, then loop. If yes, then quit.
quit: ;here ax will hold the value of 1+2+...+10 .

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-10 (CONT…)

Example: Write an assembly language program to Factorial of a number.

mov cx, 8 ; Again, CX becomes the counter

mov ax, 1 ; Since mul instruction uses DX:AX register
pair
mov dx, 0 ; We use them to hold our factorial product.
; We initially set it to 1
myloop:
mul cx ; DX:AX = AX * CX
dec cx ; decrement counter
cmp cx, 0
jne myloop
quit: ; Here DX: AX will hold the value of the
factorial

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-11

Bus Timing Diagram of 8086

8086 BUS CYCLE

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-11 (CONT…)

8086 READ/WRITE CYCLE

MINIMUM MODE

READ CYCLE WRITECYCLE

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12

Input/output (I/O) and device Interfacing

Input/output Instructions in 8086 CPU

The 8086 microprocessor can access information from ports as well as from the memory.
There are two instructions for this purpose “IN” and “OUT”.
Case 1: 8-bit data ports Case 2: 16-bit data ports
Inputting Data Outputting Data Inputting Data Outputting Data
Format IN dest, source OUT dest, Format IN dest, source OUT dest, source
source
(1) IN AX, port# OUT port#, AX
(1) IN AL, port# OUT port#, AL
(2) MOV DX, port# MOV DX, port#
(2) MOV DX, port# MOV DX, port#
IN AX,DX OUT DX,AX
IN AL,DX OUT DX,AL

Example: Assume that AX=98F6H and the output port address is 47H, then
OUT 47H, AX
 In the above case F6H, the content of AL, goes to port address 47H and 98H, the
content of AH goes into the port address 48H.
 In other words the low byte goes to the low port address, and the high byte goes to
the high byte address. 76
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12 (CONT...)

Timings and Delays

ln the real time applications, such as traffic light control, digital dock, process
control, serial communication, it is important to keep a track with time.
 In traffic light control application, it is necessary to give time delays
between two transitions.
 Microprocessor takes fixed time as per the instruction, since it is driven
by constant frequency clock.

NOP Instruction
 NOP instruction does nothing
 takes 3 clock cycles of processor time to execute.
 Executing NOP instruction in between two instructions we can get delay of
3 clock cycle.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12 (CONT...)

Timer Delay using Counters

Clock cycles required
MOV CX, COUNT ; Load Count 4
BACK: DEC CX ; Decrement count 2
JNZ BACK ; If count≠0, repeat 16/4
 Two values are specified for the number of cock cycles for the JNZ
instruction.
 The smaller value is applied when the condition is not met [count≠0]
 the larger value is applied when it is met [count=0]
Total dock cycles required to execute the given program

For count = 100, the number of cock cycles required are

= 4 + (100- 1) X (2 + 16) + (2 + 4)= 1792
Assuming operating frequency of 8086 system 10 MHz,
Time required for one clock cycle= 0.1 μsec
Total time required for execution with count equal to 100 is =179.2 μsec
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12 (CONT...)

Timer Delay using Nested Loops

MOV BX, Multi count ; Load multiplier count
REPE: MOV CX, COUNT ; Load Count
BACK: DEC CX ; Decrement count
JNZ BACK ; If count≠0, repeat
DEC BX ; Decrement multiplier count
JNZ REPE ; If not zero repeat

Total dock cycles required to execute the given program

For count = 100 and multiplier count 50, the number of dock cycles required
are = [ 4 + (100 - 1)×(2 + 16)+ (2 + 4)]× 50 = 89600
Assuming operating frequency of 8086 system 10 MHz .Total time required for
execution of a given program = 89600 x 0.1 μsec = 8.96 ms

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12 (CONT...)

Example: Write an 8086 ALP to generate a delay of 100ms, if 8086 system

frequency is 10 MHz.

MOV CX, COUNT ; Load Count 4

BACK: DEC CX ; Decrement count 2
JNZ BACK ; If count≠0, repeat 16/4

80
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12 (CONT...)

Peripheral Devices

8253 / 8254 Timer

 Designed to solve one of the most common problems in any microcomputer system, the
generation of accurate time delays under software control.
 Instead of setting up timing loops in software, the programmer configures the 8254 to
match his requirements and programs one of the counters for the desired delay.

4 port address needed for a single 8253/8254

CS A1 A0 Selects:

0 0 0 Counter 0
0 0 1 Counter 1
0 1 0 Counter 2
0 1 1 Control Register

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-12 (CONT...)

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13

8253 / 8254 Timer Control Word Format

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13

 Each of the three counter has 3 pins associated

– CLK: input clock frequency
• A square wave of 33% duty cycle
• 8253: 0 ~ 2 MHz, 8254: 0 ~ 8 MHz
– OUT: can be square wave, or one shot
– GATE: Enable (high) or disable (low) the counter

 Data Pins: (D0 ~ D7)

– Allow the CPU to access various registers inside the 8253/54 for both read
and write operations. RD and WR are connected to IOR and IOW of control
bus.

 Each of the three counters must be programmed separately

 Control byte must be first written into the control register. The 8253/54
must be initialized before use
 The programmer can not only write the value of the divisor into the
8253/54, but read the content of the counter at any given time as well
 All counters are down counters.
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13

Shape of the 8253/54 Output

• Given CLK = 1.193 MHz, the clock period of input

frequency is 838 ns

• If the number N loaded into the counter is even, both

high and low pulse are the same length, which is N/2 *
838 ns

• If the number N loaded into the counter is odd, the high

pulse is (N+1)/2 * 838 ns and the low pulse is (N–1)/2 *
838 ns

•  If N is odd, the high portion of the output square

wave is slightly wider than the low portion
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

8253/54 Operation Modes

There are 5 modes of operation

• Mode 0: Interrupt on terminal count

• Mode 1: HW triggered / programmable one shot
• Mode 2: Rate Generator (Divide-by-N counter)
• Mode 3: Square wave rate generator
• Mode 4: Software triggered strobe
• Mode 5: Hardware triggered strobe

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

8253/54 Operation Modes

• Mode 0: Interrupt on terminal count

– The output is initially low, and remain low for the duration of
the count if GATE=1. When the terminal count is reached, the
output will go high and remain high until a new control word or
new count number is loaded
• Width of low pulse = N * T, where T is clock period

– Example: GATE=1 and CLK = 1 MHz

Clock count N = 1000

– If GATE becomes low at the middle of the count, the count will
stop and the output will be low. The count resumes when the
GATE becomes high again  This in effect adds to the total
time the output is low.
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

8253/54 Operation Modes

• Mode 1: HW triggered / programmable one shot

– The triggering must be done through the GATE input by sending a 0-
to-1 pulse to it.
– Steps: 1) Load the count register
2) A 0-to-1 pulse must be sent to the GATE
input to trigger the count

– In Mode 1, after sending the 0-to-1 pulse to GATE, OUT becomes

low and stays low for a duration of N*T, then becomes high and
stays high until the GATE is triggered again
– If during the activation, a retriggered happened, then restart the
down counting

• Mode 2: Rate Generator (Divide-by-N counter)

– In Mode2, if GATE=1, OUT will be high for N*T, goes low only for
one clock pulse, then counter is reloaded automatically, and the
process continues indefinitely.  Whole period: (N+1) * T 88
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

8253/54 Operation Modes

• Mode 3: Square wave rate generator

– Most commonly used

• Mode 4: Software triggered strobe

– Similar to Mode2, except that the counter is not reloaded automatically
– In Mode4, if GATE=1, the output will go high when loading the count, it
will stay high for duration N*T. After the count reaches zero, it
becomes low for one clock pulse, then goes high again and stays high
until a new command word or new count is loaded
– To repeat the strobe, the count must be reloaded

• Mode 5: Hardware triggered strobe

– Similar to Mode4, except that the triggering must be done with the GATE input
– The count starts only when a 0-to-1 pulse is sent to the GATE input
– If GATE retriggered during the counting, it will restart the down counting

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

Example: Write a program to generate a square wave of 1 KHz

frequency on OUT 1 pin of 8253/54. Assume CLK1 frequency is 1MHz
and address for control register =0BH, counter1 = 09H and counter 2 =
0AH.
Solution: To get square wave mode 3 is selected count should be
SC1 SC0 RW1 RW1 M2 M1 M0 BCD
= 77H
0 1 1 1 0 1 1 1

Source program

MOV AL, 77H

OUT 0BH, AL ; Loads control word (77H) in
; the control register.
MOV AL, 00H ; loads lower byte (00) of the count
OUT 09H, AL
MOV AL, 10 ; Loads higher byte (10) of the count
OUT 09H, AL 90
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

Example: consider a gate input waveform of 1 KHz, clock input of 1.5 MHz (T=0.66)Write a
ALP to gives a Low output pulse of 0.2 msec. from the counter 0 only when the gate is given a
low to high transition. Applying a 1 KHz signal at the gate input and draw the output waveform
at OUT 0. The low pulse not produce when the count is loaded in the count register- it starts
only when a low to high transition occurs on the gate.

Solution: To calculate the count value

Control word is: 00110010=32H
CR EQU 0CEH ; address of control register
CNT0 EQU 0C8H ; address of counter 0
MOV AL, 32h ; control word for mode 1 CNT0
OUT CR, AL ; send it to control register
MOV AX, 12FH ; load count in AX
OUT CNT0, AL ; send LSB of count to counter0
MOV AL, AH ; move AH to AL
OUT CNT0, AL ; send MSB of count to counter0
END

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

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Lecture-13 (CONT...)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-13 (CONT...)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-14

The 8255 programmable Peripheral Interface (PPI)

 designed to permit easy implementation of

parallel I/O into the microcomputer
 Most widely used I/O chips
 It has three separately accessible ports, A, B,
and C
 User can program the individual ports to be
input or output, and change the dynamically

The block diagram of the 8255 Chip

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-14 (CONT...)

Detailed Block Diagram of 8255

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-14 (CONT...)

Detailed Pin layout of 8255 100

 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-14 (CONT...)

Programming Modes of PPI:

Mode 0: Simple input or output mode:

The salient features of this mode are as listed below:

1. Two 8-bit ports (port A and port B)and two 4-bit ports (port C upper and lower)
are available. The two 4-bit ports can be combinedly used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configuration are
possible.
• All these ports can be selected by programming a register internal to 8255
known as CWR.
• The control word register has two formats. The first format is valid for I/O
modes of operation, i.e. modes 0, mode 1 and mode 2 while the second format is
valid for bit set/reset (BSR) mode of operation.
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Lecture-14 (CONT...)

Programming Modes of PPI:

Mode 1: I/O with handshaking handshake capability:

In this mode the handshaking control the input and output action of the specified port. Port
C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes
port B and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-
PC5 provide strobe lines for port A.

This group including port A and PC3-PC5 from group A. Thus port C is utilized for
generating handshake signals. The salient features of mode 1 are listed as follows:
1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and
outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and
PC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may
be used as independent data lines.
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-14 (CONT...)

Programming Modes of PPI:

Mode 2: Bi-directional I/O with handshaking/ Strobed bidirectional I/O :

This mode of operation of 8255 is also called as strobed bidirectional I/O. This mode of
operation provides 8255 with an additional features for communicating with a peripheral
device on an 8-bit data bus. Handshaking signals are provided to maintain proper data flow
and synchronization between the data transmitter and receiver. The interrupt generation and
other functions are similar to mode 1.

In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rd and WR
signals decide whether the 8255 is going to operate as an input port or output port.

The Salient features of Mode 2 of 8255 are listed as follows:

1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3. Three I/O lines are available at port C.(PC2 – PC0)
4. Inputs and outputs are both latched.
5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake
signals for the 8-bit data transfer on port A. 103
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-15

Control Word(CW):

For Port B

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-15

Port Address for The 8255 PPI

The port Addresses for the 8255 Example: The 8255 shown in Figure below configured as follows:
Port A as Input, Port B as Output, and all the bits of port C as
Port Address A0 A1 Output.
A 300H 0 0 a) Find the port address assigned to A, B, C and Control register
B 301H 0 1 b) Find the control byte (word) for this configuration.
C 302H 1 0 c) Program the ports to input data from port A and send it to
Control 303H 1 1 both port B and C.
Register

The control word is 90H or 1001 0000.

MOV AL, 90H
MOV DX, 313H
OUT DX, AL Port/Control Register Address line Address
MOV DX, 310H
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
IN AL,DX
Port A 0 0 1 1 0 0 0 1 0 0 0 0 310h
MOV DX,311H
OUT DX, AL Port B 0 0 1 1 0 0 0 1 0 0 0 1 311h
MOV DX, 312H Port C 0 0 1 1 0 0 0 1 0 0 1 0 312h
OUT DX,AL Control Register 0 0 1 1 0 0 0 1 0 0 1 1 313h
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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-15

Example: Configure the ports of 8255 as follows: port A=input, B=output/ PC0 –
PC3=input, and PC4-PC7=output. Determine the content of the Control Register
and, Program the 8255 to get data from port A and send it to port B. In addition,
input data from PCL and send out to PCU. (PCL=Lower 4 bits (nibble) of Port C,
PCU; Upper 4 bits (nibble) of Port C) (Assume the standard port addresses of 8255
given above)
D7 D6 D5 D4 D3 D2 D1 D0
Control Word: 1 0 0 1 0 0 0 1 = 91H
MOV AL, 91H ; this control byte is used to initialize the PPI
MOV DX, 303H ; get the address of Control Register
OUT DX, AL ; output the Control Byte to the Control register
MOV DX, 300H ; get the address of Port A
IN AL, DX ; input data from Port A
MOV DX, 301H ; get the address of Port B
OUT DX, AL ; output data to Port B
MOV DX, 302H ; get the address of Port C
IN AL, DX ; get the data from Port C
AND AL, 0FH ; mask the upper bits
MOV CL, 4 ; rotate count =4
ROL AL, CL ; shift the bits to upper position
106
OUT DX, AL ; output PCL to PCU
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-15

Example: For the following configuration find the port address assigned to A, B, C
and Control register

Solution:

Exercise: write an ALP that will input the contents of port B and port C, and then
perform ANDing and output the result to port A. Port A is connected with address
10600h.
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-16

Interfacing
problem:
Example 1: write an assembly language program to generate a square wave of frequency
1Hz on the PC2 pin of the 8255 PPI having Port A address at 7000h.

Solution:
The given frequency is 1Hz.
So,
So, TON =TOFF =500ms
The Port A address is 7000h, so the address of CWR is 7006h

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-16 (CONT...)

CW:
0 X X X A2 A1 A0 S/R
0 0 0 0 0 1 0 1 =05H= = PC 2 Set
0 0 0 0 0 1 0 0 =04H= = PC 2 Reset

MOV AX, 3000h

MOV SS, AX ; Initialize stack memory segment
MOV SP, 0200h
MOV DX, 7006h ; Initialize port address7006h in DX register
MOV AL, 04h
OUT DX, AL ; Reset PC2 pin of port C
L1: MOV AL, 05h
OUT DX, AL ; set PC2 pin of port C
CALL DELAY ; Delay of 500ms
DEC AL/MOV AL, 04h ; AL=04h
OUT DX, AL ; Reset PC2 pin of port C
CALL DELAY ; Delay of 500ms
JMP L1
HLT/INT3
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-16 (CONT...)

Example 2: write an assembly language program to generate low-level active pulse

on PC0 pin of the 8255 PPI, connected with the even bank, having port A address at
2008H.Pulse ON time is 1s.

The control word format to set and reset

PC0 pin of port C is given below:

The address of port A is 2008H, so the address of control word register CWR is 200Eh.
MOV AX, 3000h OUT DX, AL; Set PC0 pin of port C
MOV SS, AX; Initialize stack memory segment MOV AL, 00h
MOV SP, 0100h OUT DX, AL; Reset PC0 pin of port C
CALL DELAY; Delay of 1s
MOV DX, 200Eh; Transfer 16-bit port address MOV AL, 01h
in DX register OUT DX, AL; Set PC0 pin of port C
MOV AL, 01h HLT/INT3

When interface with 8086 then A1 and A2 pins of 8086 connected with A0 and A1 pins of 8255.
When interface with 8088 then A0 and A1 pins of 8088 connected with A0 and A1 pins of 8255.
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Lecture-16 (CONT...)

Example 3: Write an assembly language program to read the settings of 12 switches

which are connected to the 8255 and display it on LEDs.
Use the control word to configure the ports of
an 8255 chip in Mode 0, with port B and port
Port C upper (PCU) as inputs and port A and
Port C lower(PCL) as outputs.
Use Port A address=C0h
B address=C2h
C address=C4h
CR address=C6h
When a switch is closed, a ‘0’ is read in, and
when it is open, a ‘1’ is read into the Port lines.

To the pins of Port A and Port CL, connect 12 LEDs along with their current
limiting resistors. The LEDs glow when the corresponding pins have a high logic
on them.
a) Control register:
=8Ah
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-16 (CONT...)

Programming steps:

 The ports and the control register address have been given labels and will be
specified using the EQU directive. Since the Port addresses are 8-bit long,
fixed port addressing can be used.

 The switch settings at the input port B can be read in directly and transferred
to the output port A.

 The data at Port CU can be read in by inputting Port C fully, but the switch
settings will be available only at the upper 4-bits position and have to be
shifted to the position of the lower 4-bits to output it to the LEDs.

Program: Home Work

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-17

Prob:2 Find the address of PA, PB, PC and CR of the following configuration:

N.B: Rest of related mapping Contain in soft copy.

File name:
(A.P Godse) Ch 9 Part-1.pdf
(A.P Godse) Ch 9 Part-2.pdf

Note:
When interface with 8086 then A1 and A2 pins of 8086
connected with A0 and A1 pins of 8255.

When interface with 8088 then A0 and A1 pins of 8088 Fig: I/O Mapped I/O with 8086.
connected with A0 and A1 pins of 8255.

Port/Control Register Address line Address

A7 A6 A5 A4 A3 A2 A1 A0
Port A 0 0 0 0 0 0 0 0 00h
Port B 0 0 0 0 0 0 1 0 02h
Port C 0 0 0 0 0 1 0 0 04h
Control Register 0 0 0 0 0 1 1 0 06h
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-17 (CONT...)

Stepper Motor Control

Stepper motors are used for position control applications, such as for the control of the disk drives
and in robotics.
 The most common stepper motors have four stator windings that are paired with a center
tapped common shown in Figure below (Figure of the textbook)

 While the conventional motor shaft runs freely, the stepper motor shaft moves in a fixed
repeatable increment, which allows one to move it to a precise position.

Fig: Rotor alignment of the stepper motor. Fig: Stator windings configuration

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-17 (CONT...)

Stepper Motor Control

Normal 4-Step Sequence

Clockwise Step # Winding A Winding B Winding C Winding D Counter

Clockwise
I 1 1 0 0 1 /\
I 2 1 1 0 0 I
I I
3 0 1 1 0
\/ I
4 0 0 1 1

The table above shows a normal 4-step Sequence. Note that once, we start with
any of the sequences in Table below (i.e. step 3 [0110] ) we must continue in the
sequence of steps, 4, 1, 2, and so on.

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-17 (CONT...)

Example: Given the 8255 connection to the stepper motor of Figure below,
- code a program to rotate it continuously.
- press any key on the IBM PC keyboard to stop it.
(Assume that the 8255 PPI is located at 300H) Use Port A as the output port.

Control word:

= 80H
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-17 (CONT...)

MAIN: MOV AL, 80H ; control word for all 8255 ports as out
MOV DX, 303H ; control register address of 8255
OUT DX, AL ; to control register
MOV BL,66H ; or BL=33H, BL=99H or BL=CCH
AGAIN: MOV AH, 01 ; check the key press
INT 16H ; using INT 16
JZ EXIT ; stop if any key pressed
MOV AL, BL ; otherwise send pulse to the stepper motor
MOV DX, 300H ; port A address of 8255
OUT DX, AL
MOV CX, 0FFFFH ; (change this value to see rotation speed)
Call Delay ; set delay
ROR BL, 1 ; rotate for the next step
JMP AGAIN ; and continue until a key is pressed
EXIT:
END MAIN 117
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-18

8086 MEMORY & MEMORY DEVICES

Types of Memory Devices

Memory

ROM
RAM

EPROM PROM

EEPROM UVEPROM

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-18 (CONT...)

Sl. EEPROM UVPROM

No.

1. Can be erased and programmed with 1. Can be erased and programmed with
electrical signals. ultraviolet light.

2. The voltage on the floating gate structure allows 2. The photo current from the insulated
storage of information. gate structure allows storage of information.

3. Higher speed of operation. 3. Lower speed of operation.

4. More expensive. 4. Less expensive.

5. Relatively easy to manufacture. 5. Relatively difficult to manufacture.
6. Erasing takes several minutes. 6. Erasing takes several minutes.
7. In-situ erasing possible. 7. In-situ erasing not possible.
8. Byte wise erasing possible. 8. Erasing wipes out the entire memory.
9. Less packing density. 9. More packing density.
Applications: BIOS, Memory for digital cameras
and MP3 audio players, USB storage devices

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-18 (CONT...)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19

Memory Address Decoding

8088: 8 x 2764 = 8 KB x 8 = 64 KB
Memory address space: F0000 – FFFFF

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

Concept of Memory interfacing

 Microprocessor 8086/88 can access 1Mbytes memory since address bus

is 20bit.
 EPROP used as a program memory and RAM as data memory. When both,
EPROM and RAM are used, the total address space 1Mbytes shared by
them.
 We can place EPROM/RAM in anywhere in full 1Mbytes of memory.
 While interfacing with 8086 we have to provide odd and even bank of
memory. Even bank is selected when A0=0 and odd bank is selected
when BHE=0.
 Odd bank and even banks are not require for interfacing memory to
8088.

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

Memory interfacing
Example: Interface the following Memory ICs with 8086
i) Two 4KB EPROMs ending at FFFFFH
ii) Two 4KB SRAMs starting at 00000H

i) Given the ending address of EPROMS = FFFFF

Then their starting address is = FFFFF (24KB)
= FFFFF (24)
= FDFFF (add 1) to include
FFFFF
= FE000
Address range of even EPROMS =FE000 --- FFFFE
Address range of odd EPROMS =FE001 --- FFFFF

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

ii) Given starting address of two 4KB SRAMS = 00000H

Then their ending address is = 00000 (24KB)
= 02000H (subtract 1) because address started at 00000H
=1FFFF
Address range of even SRAM = 00000 --- 01FFE
Address range of odd SRAM = 00001 --- 01FFF
Once the address range of each chip decided, create binary table for each address. This is necessary to
generate
i) chip select signal
ii) decoder select signals (G1,G2A,G2B)

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

Table-1
ICs Address A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Odd FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM
FE001 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1
Even FFFFE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
EPROM
FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Odd 01FFF 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
SRAM 00001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Even 01FFE 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0
SRAM 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table-2
Bit Chip select
A19 0 SRAM
1 EPROM
A0 0 Either even EPROM or even SRAM
1 Either odd EPROM or odd SRAM
BHE 0 Either even + odd or odd only
1 Even only
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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

Table-3 (Truth Table)

A19 A0 BHE Dec. Chip select

value
0 0 0 0 Both SRAM
0 0 1 1 Even SRAM
0 1 0 2 Odd SRAM
0 1 1 3 Not use
1 0 0 4 Both EPROM
1 0 1 5 Even EPROM
1 1 0 6 Odd EPROM
1 1 1 7 Not use

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

Based on the above truth table draw the logic diagram to generate unique chip select signals

Exclusive-NOR (Truth table) Chip select logic diagram

X (Input 1) Y (Input 2) Z (Output)
0 0 1
0 1 0
1 0 0
1 1 1

Note to students:
solution to this kind of question should only include following things. Rest is confined to rough work.
i) Address calculation for each chip
ii) Binary table
iii) Final diagram containing Processor, memory chips, chip selection logic diagram, hardware connection

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-19 (CONT...)

Complete diagram to interface two 4KB EPROMS and two 4KB SRAMS to 8086

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20

Interfacing A/D Data Converters

ADC 0808/0809:

Fig: Block Diagram of ADC 0808 / 0809. 129

 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20(CONT...)

Pin Diagram:

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20 (CONT...)

Analog I/P Address lines Example: Interfacing ADC 0808 with 8086
selected
using 8255 ports. Use port A of 8255 for
C B A transferring digital data output of ADC to the
I / P0 0 0 0
CPU and port C for control signals. Assume that
I/P1 0 0 1
I/P2 0 1 0
an analog input is present at I/P2 of the ADC
I/P3 0 1 1 and a clock input of suitable frequency is
I / P4 1 0 0 available for ADC.
I/P5 1 0 1
I/P6 1 1 0
I/P7 1 1 1

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Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20 (CONT...)
D7 D6 D5 D4 D3 D2 D1 D0
The required ALP is as follows: 1 0 0 1 1 0 0 0

MOV AL, 98h ; initialize 8255 as

OUT CWR, AL ; discussed above.

MOV AL, 02h ; Select I/P2 as analog

OUT Port B, AL ; input.

MOV AL, 00h ; Give start of conversion

OUT Port C, AL ; pulse to the ADC

MOV AL, 01h

OUT Port C, AL

MOV AL, 00h

OUT Port C, AL

WAIT: IN AL, Port C ; Check for EOC by

RCR ; reading port C upper and

JNC WAIT ; rotating through carry.

IN AL, Port A ; If EOC, read digital equivalent in AL

HLT ; Stop 132

 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20 (CONT...)

Interfacing Digital to Analog Converters

Pin Diagram: EXAMPLE: Interfacing DAC AD7523 with an
8086 CPU running at 8MHZ and write an
assembly language program to generate a
sawtooth waveform of period 1ms with Vmax
5V.

Fig: Interfacing of AD7523 133

 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20 (CONT...)

Interfacing Digital to Analog Converters

Resolution
START: MOV AL, 80h ; make all ports output
Input Digital Number, X = Total output voltage/Resolution
OUT CW, AL
AGAIN: MOV AL, 00h ; start voltage for ramp
BACK: OUT PA, AL
INC AL
CMP AL, 0FFh
JB BACK
JMP AGAIN
END START

Exercise: Write a program to generate an analog

signal at the output of 8-bit DAC having reference
voltage 2.56 V. The required analog signal is shown in
the figure given

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-20 (CONT...)

= 2.56 v
Digital input of DAC is of 8 bits, so n = 8
So, resolution ==2.56/256=10𝑚𝑉

So, if the digital input of DAC is increased by one, then analog output voltage will be
increased by 10 mV. It is called resolution.
To obtain 1V at DAC output, we have to input digital number X, where
X = Total output voltage/Resolution
X=1V/10mV=100
X=(100)D = (64)H
To transfer digital number from (100)D to (1)D in 100 ms that is 100 numbers in 100 ms. So, time required in
transferring one number
= Total time /total number
=100ms/100=1ms/Number

MOV AL, 8Oh

MOV DX, 0006h
OUT DX, AL
MOV DX, 0000h
L2: MOV AL, 64h ; as voltage decreases 1V to 0V with time, so, starting countdown.
Ll : OUT DX, AL
CALL DELAY 1 ; delay of 1ms
DEC AL
JNZ L1
OUT DX, AL
CALL DELAY2 ; delay of 100ms
135
JMP L2
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-21

BUS STANDARDS
BUS: A bus connects all the internal computer components to the CPU and Main
memory. A fast bus allows data to be transferred faster, which makes applications run
faster.
BUS

System Bus
I/O Bus

Address Bus Control Bus

ISA, Micro Channel
(MCA), EISA, VESA Local
Data Bus
bus (VL-bus), PCI Local
bus, AGP, USB.

136
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-22

PCI BUS
PCI (Peripheral Component Interconnect) bus is the standard I/O bus found in Pentium
systems and it was developed by Intel in 1993 to replace the various busses which had
been in use on both PCs and Macintoshes. A PCI interface contains a series of register,
located in a small memory device on the PCI interface, which contains information
about the board. The information in these registers allows the computer to automatically
configure the PCI card.

Feature of PCI Bus:

 Plug and Play
–The PCI interface contains 256-bytes configuration

 Bus Width
– PCI may be implemented with a 32 or 64-bit data bus.

 Bus Speed
– PCI may use a clock speed of 33Mhz or 66Mhz 137
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-22 (CONT...)

 Bus Throughput
– PCI maximum throughput ranges from 132MB/s to 538MB/s.

 Access Time
– PCI access time can be as fast as 60ns when implemented with a
33Mhz clock.
 Devices Per Bus
– The PCI specification provides support for up to 10 physical devices
and 80 logical devices per PCI bus.
 Number of Busses
– The PCI specification provides support to up to 256 PCI bus
implementations within a computer system.
 Burst Transfers
– The PCI specification provides support for burst transfers.

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 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-22(CONT...)

Bus structure of Intel Pentium

Pentium
CPU

CPU bus: fast (100 MHz, 64 bits) [10 nsec./cycle]

PCI
Cache Memory
Controller

PCI bus: fast (33 MHz, 32/64 bits) [30 nsec./cycle]

Video System
Disk
Adapter ROM

Expansion
Bus
Controller

ISA bus: slow (8 MHz, 8/16 bits) [125 nsec./cycle]

Serial Parallel Floppy

RTC Keyboard
Port Port Disk

Fig: the system block diagram for the personnel computer that contain a PCI bus. 139
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-23

USB
Universal Serial Bus was born to overcome the limitation of wide range of peripheral
interface using Centronics parallel and RS-232 serial port interface. USB is fast and
flexible for connecting all kinds of peripherals
USB system

USB host USB cable

USB device
Data
Rates:
Low-­‐speed & full-­‐speed High speed: 480 Mbps (USB 2.0)
 Frame rate:1000Hz  Microframe rate:8000Hz
 Low-­‐speed:1.5 Mbps 53,000bits per microframe (practically)
1,200 bits per frame (practically) Super speed (USB3.0): approx.4.8Gbit/s
 Full speed:12Mbps
12,000 bits per frame 140
 T. H. M. Sumon Rashid
Introduction to Microprocessor Asst. Prof., EEE, PUST
Lecture-23(CONT...)

Features and advantages of USB

Universal serial bus is a plug-and-play facility and connects a host computer to many
simultaneously accessible peripheral devices.
The characteristics associated with universal serial bus are:
– Master/slave, half-duplex, timed communication bus system and is
designed to connect peripherals and external hubs.
– Master or host hub has complete control over transaction.
– Peripherals cannot initiate a communication on the USB bus.
– Supports data transfer rates up to 480 Mbps.
Application areas of USB:
– Easy to set up and configure.
Depending on the data transfer rates, the universal
– Plug and play feature. serial bus supports a lots of application areas.

Note: For more advantage and application follow class .

THE END
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