MODULE - 4

8051 ARCHITECTURE
INTRODUCTION TO
INTEL MCS 51 µC

1
 INTEL MCS 51 MICROCONTROLLER

 The Intel MCS-51 (commonly termed 8051) is a Harvard

architecture, complex instruction set
computing (CISC) Architecture, single
chip microcontroller (µC) series developed by Intel in 1980
for use in embedded systems

 Intel's original MCS-51 family was developed using N-type

metal-oxide-semiconductor (NMOS) technology

 But later versions, identified by a letter C in their name

(e.g., 80C51) used complementary metal–oxide–semiconductor
(CMOS) technology and consume less power

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 INTEL MCS 51 MICROCONTROLLER
FEATURES
 8-bit CPU
 64K bytes on-chip program memory (ROM)
 128 bytes on-chip data memory (RAM)
 32 I/O pins arranged as four 8-bit ports (P0 - P3)
 32 general purpose registers each of 8-bit
 Special Function Registers (SFRs) of 128 bytes
 16-bit Program Counter
 8-bit Processor Status Word (PSW) & Stack Pointer
 Two 16-bit timer/counters : T0 and T1
 Two external and three internal vectored interrupts
 One full duplex serial I/O (UART)
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 INTEL MCS 51 MICROCONTROLLER

8051 FAMILY SERIES

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 INTEL MCS 51 MICROCONTROLLER

8051 FAMILY SERIES

 Although the 8051 is the most popular member of the 8051
family, you will not see “8051″ in the part number.

 This is because the 8051 is available in different memory

types, such as UV-EPROM, flash, and NV-RAM, all of which
have different part numbers.

 The UV-EPROM version of the 8051 is the 8751. The flash

ROM version is marketed by many companies including Atmel
Corp. and Dallas Semiconductor.
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 INTEL MCS 51 MICROCONTROLLER

8051 FAMILY SERIES

 The Atmel Flash 8051 is called AT89C51, while Dallas

Semiconductor calls theirs DS89C4xO (DS89C420/430/440).

 The NV-RAM version of the 8051 made by Dallas

Semiconductor is called DS5000.

 There is also an OTP (one-time programmable) version of the

8051 made by various manufacturers.

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 INTEL MCS 51 MICROCONTROLLER

8051 MAJOR MANUFACTURERS

 ATMEL
 ANALOG DEVICES
 ST MICROELECTRONICS
 DALLAS
 MAXIM
 SILICON LABS
 TEXAS INSTRUMENTS
 MICROCHIP
 ZILOG
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 INTEL MCS 51 MICROCONTROLLER

8051 ATMEL SERIES

Part Number ROM RAM I/O pins Timer Interrupt Vcc Packaging
AT89C51 4K 128 32 2 6 5V 40
AT89C52 8K 256 32 3 8 5V 40
AT89C1051 1K 64 15 1 3 3V 20

AT89C2051 2K 128 32 3 8 3V 20
AT89LV51 4K 128 32 2 6 3V 40
AT89LV52 8K 128 32 3 8 3V 40

MODULE - 2 8
 8051
MICROCONTROLLER
PIN DETAILS
 8051 MICROCONTROLLER PIN DETAILS

8051 PIN DETAILS

 Although 8051 family members (e.g., 8751, 89C51, 89C52,
DS89C4xO) come in different packages, such as DIP (dual in-
line package), QFP (quad flat package), and LLC (leadless chip
carrier)

 They all have 40 pins that are dedicated to various functions

such as I/O, RD, WR, address, data, and interrupts.

 Some companies provide a 20-pin version of the 8051 with a

reduced number of I/O ports for less demanding applications.
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 8051 MICROCONTROLLER PIN DETAILS

8051 PIN DETAILS

 However, since the vast majority of developers use the 40-
pin chip, we will concentrate on that.
 In 40 pin package, a total of 32 pins are set aside for the
four ports PO, P1, P2, and P3, where each port takes 8 pins.
 The rest of the pins are designated as Vcc, GND, XTAL1,
XTAL2, RST, EA, PSEN, and ALE.

MODULE - 2 10
 8051 MICROCONTROLLER PIN DETAILS

8051 PIN DETAILS

 Of these pins, six (Vcc, GND, XTAL1, XTAL2, RST, and EA)
are used by all members of the 8051 and 8031 families.

 In other words, they must be connected in order for the

system to work, regardless of whether the microcontroller is
of the 8051 or 8031 family.

 The other two pins, PSEN and ALE, are used mainly in 8031-
based systems.

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 8051 MICROCONTROLLER PIN DETAILS

8051 SCHEMATICS

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 8051 MICROCONTROLLER PIN DETAILS

8051 PIN DIAGRAM

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 8051 MICROCONTROLLER PIN DETAILS

8051 PIN DESCRIPTION

 Pin-40 : Vcc is the main power source. Usually its +5V DC.

 Pins 32-39: Port 0 (P0.0 to P0.7) – In addition to serving as

I/O port, lower order address and data bus signals are
multiplexed with this port (to serve the purpose of external
memory interfacing). This is a bi directional I/O port (the
only one in 8051) and external pull up resistors are required
to function this port as I/O.

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 8051 MICROCONTROLLER PIN DETAILS

 Pin-31:- ALE - Address Latch Enable. It is especially used

for 8031 IC to connect it to the external memory. It can be
used while deciding whether P0 pins will be used as Address
bus or Data bus. When ALE = 1, then the P0 pins work as
Data bus and when ALE = 0, then the P0 pins act as Address
bus.

 Pin-30:- EA - External Access input is used to enable or

disallow external memory interfacing. If there is no external
memory requirement, this pin is pulled high by connecting it
to Vcc.
MODULE - 2 15
 8051 MICROCONTROLLER PIN DETAILS

 Pin- 29:- PSEN or Program Store Enable. This is an active

low pin, i.e., it gets activated after applying a low pulse. It
is an output pin and used along with the EA pin in 8031 based
(i.e. ROMLESS) Systems to allow storage of program code in
external ROM.

 Pins- 21-28: Port 2 (P 2.0 to P 2.7) – in addition to serving

as I/O port, higher order address bus signals are multiplexed
with this quasi bi directional port.

 Pin 20:- Vss – it represents ground (0 V) connection.

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 8051 MICROCONTROLLER PIN DETAILS

 Pins 18 and 19:- XTAL1 & XTAL2 Used for interfacing an

external crystal to provide system clock.

 Pins 10 – 17:- Port 3 (P 3.0 to P 3.7) It is also of 8 bits

and can be used as Input/Output. This port provides some
extremely important signals. P3.0 and P3.1 are RxD
(Receiver) and TxD (Transmitter) respectively and are
collectively used for Serial Communication. P3.2 and P3.3 pins
are used for external interrupts. P3.4 and P3.5 are used for
timers T0 and T1 respectively. P3.6 and P3.7 are Write
(WR) and Read (RD) pins.

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 8051 MICROCONTROLLER PIN DETAILS

 Pin 9:- RESET pin is used to set the 8051 microcontroller to

its initial values, while the microcontroller is working or at
the initial start of application. The RESET pin must be set
high for 2 machine cycles.

 Pins 1 – 8:- Port 1 (P 1.0 to P 1.7). It is an 8-bit port (pin

1 through 8) and can be used either as input or output.
Unlike other ports, this port does not serve any other
functions. Port 1 is an internally pulled up, quasi bi
directional I/O port.

MODULE - 2 18
 8051
MICROCONTROLLER
ARCHITECTURE
 8051 MICROCONTROLLER
ARCHITECTURE
8051 ARCHITECTURE (Simplified)

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 8051 MICROCONTROLLER
ARCHITECTURE

8051
ARCHITECTURE
(Detailed)

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 8051 MICROCONTROLLER
ARCHITECTURE
CENTRAL PROCESSING UNIT (CPU)
 Central Processor Unit (CPU) is the brain of any processing
device of the microcontroller.

 It monitors and controls all operations that are performed on

the Microcontroller units.

 The User has no control over the work of the CPU directly.

 It reads program written in ROM memory and executes them

and do the expected task of that application.
MODULE - 2 21
 8051 MICROCONTROLLER
ARCHITECTURE
INTERRUPT CONTROL
 There are five interrupt sources in 8051 Microcontroller and
interrupt control section control all these interrupts.

 Two external interrupts (INT0 & INT1), two timer (TF0 &
TF1) interrupts and one serial port (RI / TI) interrupt.

 The Microcontroller 8051 can be configured in such a way

that it temporarily terminates or pause the main program at
the occurrence of interrupt. When subroutine is completed
then the execution of main program starts as usual.
MODULE - 2 22
 8051 MICROCONTROLLER
ARCHITECTURE
RAM & ROM
 Microcontroller 8051 has 4K of Code Memory or Program
memory that is it has 4KB ROM and RAM of 128 bytes.

 The memory which is used to store the program

of Microcontroller, is known as code memory or Program
memory . It is known as 'ROM'(Read Only Memory).

 Microcontroller also requires a memory to store data or

operands temporarily. This memory is known as Data Memory
and we use 'RAM'(Random Access Memory) for this purpose.
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 8051 MICROCONTROLLER
ARCHITECTURE
BUS CONTROL
 Bus control section of 8051 is responsible for controlling the
operation of address and data bus.
 Bus: Basically Bus is a collection of wires which work as a
communication channel or medium for transfer of Data.
 Buses are of two types:
 Address Bus: Microcontroller 8051 has a 16 bit address
bus. It used to address memory locations.
 Data Bus: Microcontroller 8051 has 8 bits data bus. It
is used to carry data.
MODULE - 2 24
 8051 MICROCONTROLLER
ARCHITECTURE
CRYSTAL OSCILLATOR
 Crystal Oscillator: Since Microcontroller is a digital circuit
device, therefore it requires clock for its operation.

 For this purpose, Microcontroller 8051 has oscillator circuitry

section which works as a clock source for Central Processing
Unit.

 As the output pulses of oscillator are stable therefore it

enables synchronized work of all parts of
8051 Microcontroller.
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 8051 MICROCONTROLLER
ARCHITECTURE
I/O PORTS
 I/O Ports: To connect any external devices or peripherals we
require I/O interfacing ports in the microcontroller.

 All 8051 microcontrollers have 4 I/O ports each comprising 8

bits which can be configured as input (1) or an output (0),
depends on its logic state.

 Accordingly, in total of 32 input/output pins enabling the

microcontroller to be connected to peripheral devices are
available for use.
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 8051 MICROCONTROLLER
ARCHITECTURE
TIMERS/COUNTERS
 Timers/Counters: 8051 Microcontroller 8051 two 16-bit
timers and counters: Timer 0 and Timer 1.

 They can be used either as timers to generate a time delay

or as counters to count events happening outside the
microcontroller.

 Since the 8051 has an 8-bit architecture, each 16-bit is

accessed as two separate registers of low byte and high
byte.
MODULE - 2 27
 8051 MICROCONTROLLER
ARCHITECTURE
SERIAL PORT
 Serial port: The 8051 contains one Serial port or UART
(Universal Asynchronous Receiver Transmitter)
 The serial port is full-duplex so, it can transmit and receive
simultaneously
 Two port pins are used to provide the serial interface P3.0 is
the receive pin (RXD) P3.1 is the transmit pin (TXD)
 This serial port that can be programmed to operate in one of
four different modes and at a range of frequencies.
MODULE - 2 28
 8051 MEMORY
ORGANIZATION
(RAM-ROM ORGANIZATION)
 8051 MEMORY ORGANIZATION

 The 8051 has two types of memory and these are Program
Memory and Data Memory.

 Program Memory (ROM) is used to permanently save the

program being executed, while Data Memory (RAM) is used
for temporarily storing data and intermediate results created
and used during the operation of the microcontroller.

 Depending on the model in use (8051 microcontroller family in

general) at most a few Kb of ROM and 128 or 256 bytes of
RAM is used.
MODULE - 2 29
 8051 MEMORY ORGANIZATION
PROGRAM MEMORY (ROM)
 The 8051 has 4K (4096 locations) of internal or on-chip
ROM. And it can be expanded up to 64K.

 This is used for storing the system program. 212 = 4096,

therefore the internal ROM locations go from 000H to
0FFFH.

 Even though such an amount of memory is sufficient for

writing most of the programs, there are situations when it is
necessary to use additional memory as well.
MODULE - 2 30
 8051 MEMORY ORGANIZATION
PROGRAM MEMORY (ROM)
 EA=0 In this case, the
microcontroller completely
ignores internal program
memory and executes only
the program stored in
external memory.

 EA=1 In this case, the

microcontroller executes first
the program from built-in
ROM, then the program
stored in external memory
MODULE - 2 31
 8051 MEMORY ORGANIZATION
DATA MEMORY (RAM)
 In the MCS-51 family, 8051 has 128 bytes of internal data
memory and it allows interfacing external data memory of
maximum size up to 64K.
 So the total size of data memory in 8051 can be upto 64K
(external) + 128 bytes (internal).
 So there are 3 separations/divisions of the data memory:-
1) Register banks
2) Bit addressable area
3) Scratch pad area
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 8051 MEMORY ORGANIZATION
DATA MEMORY (RAM)

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 8051 MEMORY ORGANIZATION
DATA MEMORY – REGISTER BANKS
 Registers are used to store data or operands during executions.
Register banks form the lowest 32 bytes on internal RAM
memory.

 There are 4 register banks designated bank #0,#1, #2 and #3.

Each bank has 8 registers which are designated as R0,R1…R7.

 At a time only one register bank is selected (using RS1 & RS0
bits in PSW register) for operations and the registers inside the
selected bank are accessed using mnemonics R0..R1.. etc.

 By default register bank #0 is selected (after a system reset).

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 8051 MEMORY ORGANIZATION
DATA MEMORY – REGISTER BANKS

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 8051 MEMORY ORGANIZATION
DATA MEMORY – BIT ADDRESSABLE AREA
 The 8051 supports a special feature which allows access to
bit variables. This is where individual memory bits in Internal
RAM can be set or cleared.
 The Bit Addressable area of the RAM is 16 bytes (128 bits)
next to register banks of Internal RAM located between 20h
and 2Fh. In all there are 128 bits numbered 00h to 7Fh.
 Being bit variables any one variable can have a value 0 or 1.
A bit variable can be set with a command such as SETB and
cleared with a command such as CLR.
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 8051 MEMORY ORGANIZATION
DATA MEMORY – BIT ADDRESSABLE AREA

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 8051 MEMORY ORGANIZATION
DATA MEMORY – BIT ADDRESSABLE AREA
 Example instructions are
SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0)

 Bit addressable area is mainly used to store bit variables

from application program, like status of an output device like
LED or Motor (ON/OFF) etc.
 We need only a bit to store this status and using a complete
byte addressable area for storing this is really bad
programming practice, since it results in wastage of memory.
MODULE - 2 39
 8051 MEMORY ORGANIZATION
DATA MEMORY – SCRATCH PAD RAM
 These 80 bytes of Internal RAM memory scratch pad RAM
are available for general-purpose data storage. Scratch pad
RAM is from 30H to 7FH and this includes stack too.

 However, these 80 bytes are used by the system stack and

in practice little space is left for general storage.

 Access to this area of memory is fast compared to access to

the main memory and special instructions with single byte
operands are used.
MODULE - 2 40
 8051 MEMORY ORGANIZATION
DATA MEMORY – SCRATCH PAD RAM
 The scratch pad RAM can be accessed using direct or
indirect addressing modes.

 Examples of direct addressing:

MOV A, 6Ah ;reads contents of address 6Ah to accumulator

 Examples for indirect addressing (use registers R0 or R1):

MOV R1, #6Ah ; move immediate 6Ah to R1
MOV A, @R1 ; move indirect: R1 contains address of
Internal RAM which contains data that is moved
to A.
MODULE - 2 41
 8051 MEMORY ORGANIZATION
DATA MEMORY – SFRs (Special Function Registers)
 SFRs are accessed just like normal Internal RAM locations.

 The SFR registers are located within the Internal Memory in

the address range 80h to FFh.

 Each SFR has a very specific function. Note some of the SFR
registers are bit addressable.

 Each SFR has an address (within the range 80h to FFh) and a
name which reflects the purpose of the SFR.
MODULE - 2 42
 8051 MEMORY ORGANIZATION
DATA MEMORY – SFRs
 Although 128 byes of the SFR address space is defined only
21 SFR registers are defined in the standard 8051.

 Rest of locations are intentionally left unoccupied in order to

enable the manufacturers to further develop microcontrollers
keeping them compatible with the previous versions.

 Main function of SFR is to control timers, counters, serial

I/O, port I/O, and peripherals that are present in 8051
microcontroller.
MODULE - 2 43
 8051 MEMORY ORGANIZATION

DATA MEMORY – SFRs

register layout

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 8051 MEMORY ORGANIZATION
DATA MEMORY – SFRs

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 8051 MEMORY ORGANIZATION
SFRs A- Register

 The 21 Special Function Registers of 8051 Microcontroller are

categorized in to seven groups.

1) Math or CPU Registers: A and B

2) Status Register: PSW (Program Status Word)
3) I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3 (Port 3)
4) Pointer Registers: DPTR (Data Pointer – DPL,DPH), SP (Stack Pointer)
5) Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE and IP
6) Peripheral Data Registers: TL0, TH0, TL1, TH1 and SBUF
MODULE - 2 46
 8051 MEMORY ORGANIZATION
SFRs A- Register
 The most important of all special function register is
Accumulator which is also known as ACC or A.

 The Accumulator holds the result of most of arithmetic and logic

operations. It is also used to store 8 bit data and to hold one of
operand of ALU units during arithmetical and logical operations.

 More than half instructions used by the 8051 microcontroller use

somehow use the accumulator.

 ACC is usually accessed by direct addressing and its physical

address is E0H.
MODULE - 2 47
 8051 MEMORY ORGANIZATION
SFRs A- Register
 Accumulator is an 8-bit register and it is both byte and bit
addressable.

 To access the individual bits of accumulator, use the format

ACC.X in the instruction where “X” denotes bit to be accessed.

MODULE - 2 48
 8051 MEMORY ORGANIZATION
SFRs B- Register
 It is special 8-bit math register and it is bit and byte
accessible.
 It is used in conjunction with A register as an input operand
for ALU to perform multiplication and division operation.
 It can also be used as general purpose register to store 8-
bit data.

MODULE - 2 49
 8051 MEMORY ORGANIZATION
SFRs - PSW REGISTER
 It is 8 bit register and it is bit and byte accessible.

 It contains several status bits that reflects the status of

the operation that is being carried out in the processor.

 It has 4 conditional flags or math flags (CY, AC, OV, P)which

sets or resets according to condition of result.

 It has 3 control flags (F0, RS0, RS1) by setting or resetting

bit required operation or function can be achieved.
MODULE - 2 50
 8051 MEMORY ORGANIZATION
SFRs - PSW REGISTER

MODULE - 2 51
 8051 MEMORY ORGANIZATION
SFRs - PSW REGISTER
 CY, the carry flag: This flag is set whenever there is a carry out from
the D7 bit. This flag bit is affected after an 8-bit addition or
subtraction.

 AC, the auxiliary carry flag: If there is a carry from D3 to D4 during

an ADD or SUB operation, this bit is set; otherwise, it is cleared. This
flag is used by instructions that perform BCD (binary coded decimal)
arithmetic.

 F0, the Flag 0 : The PSW.5 and PSW.1 bits are general-purpose
status flag bits and can be used by the programmer for any purpose.
In other words, they are user definable.
MODULE - 2 52
 8051 MEMORY ORGANIZATION
SFRs - PSW REGISTER
 RS0, RS1 - Register bank select bits. These two bits are used to
select one of four register banks of RAM. By setting and clearing these
bits, registers R0-R7 are stored in one of four banks of RAM.

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 8051 MEMORY ORGANIZATION
SFRs - PSW REGISTER
 OV, overflow flag:
 This flag is set whenever the result of a signed number operation
is too large, causing the high-order bit to overflow into sign bit.
 In general, the carry flag is used to detect errors in unsigned
arithmetic operations.
 The overflow flag is only used to detect errors in signed
arithmetic operations

 P, the parity flag: The parity flag reflects the number of 1 s in the A
(accumulator) register only. If the A register contains an odd number
of 1’s, then P = 1. Therefore, P = 0 if A has an even number of 1s.

MODULE - 2 54
 8051 MEMORY ORGANIZATION
SFRs - P0, P1, P2, P3 - Input/Output Registers
 There are 4 ports with in total of 32 input/output pins are
available for connection to peripheral environment.
 So 4 Input/Output ports named P0, P1, P2 and P3 has got
four corresponding port registers P0, P1, P2 and P3. All 4
port registers are bit as well as byte addressable.
 Data must be written into port registers first to send it out
to any other external device through ports.
 Similarly any data received through ports must be read from
port registers for performing any operation.
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 8051 MEMORY ORGANIZATION
SFRs - P0, P1, P2, P3 - Input/Output Registers

MODULE - 2 56
 8051 MEMORY ORGANIZATION
SFRs - P0, P1, P2, P3 - Input/Output Registers

MODULE - 2 57
 8051 MEMORY ORGANIZATION
SFRs - P0, P1, P2, P3 - Input/Output Registers

 If a bit is cleared (0), the appropriate pin will be configured

as an output, while if it is set (1), the appropriate pin will be
configured as an input.

 Upon reset and power-on, all port bits are set (1), which
means that all appropriate pins will be configured as inputs.

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 8051 MEMORY ORGANIZATION
SFRs - DPTR REGISTER
 It is a 16 bit register used to hold address of external or
internal RAM where data is stored or result is to be stored.
 It can be divided into two 8-bit registers, DPH-data pointer
higher order and DPL-data pointer lower order.
 Each register can be used as general purpose register to
store 8 bit data and can also be used to store memory
location.
 It functions as Base register in base relative addressing mode
and indirect jump.
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 8051 MEMORY ORGANIZATION
SFRs - DPTR REGISTER

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 8051 MEMORY ORGANIZATION
SFRs - STACK POINTER
 It is 8-bit register. It is byte addressable.

 It is used to hold the internal RAM memory location

addresses which are used as stack memory.

 When the data is to be placed on stack by push instruction,

the content of stack pointer is incremented by 1.

 When data is retrieved from stack, content of stack of stack

pointer is decremented by 1.
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 8051 MEMORY ORGANIZATION
SFRs - STACK POINTER

 A value stored in the Stack Pointer points to the first free

stack address and permits stack availability.

 Upon any reset and power-on, the value 7 is stored in the

Stack Pointer, which means that the space of RAM reserved
for the stack starts at this location.

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 8051 MEMORY ORGANIZATION
PC - PROGRAM COUNTER (not a part of SFRs)

 It is used to hold 16 bit address of internal RAM, external

RAM or external ROM locations.

 The Program Counter (PC) is a 2-byte address which tells the

8051 where the next instruction to be executed from
memory.

 When the 8051 is initialized PC always starts at 0000h and is

incremented each time an instruction is executed.

MODULE - 2 63
8051 MACHINE CYCLE
 8051 MACHINE CYCLES
MACHINE CYCLES
 The CPU takes a certain number of clock cycles to execute
an instruction.

 In the 8051 family, these clock cycles are referred to

as machine cycles.

 A single machine cycle is the minimum amount of time in which

a single 8051 instruction can be executed, although many
instructions take multiple cycles.

MODULE - 2 64
 8051 MACHINE CYCLES
MACHINE CYCLES
 Pulse - One complete oscillation of the clock source; State -
Two pulses; Machine Cycle - six states.

MODULE - 2 65
 8051 MACHINE CYCLES
MACHINE CYCLES
 If an instruction takes one machine cycle to execute, it will
take 12 pulses of the crystal to execute.

 8051 is designed to operate between 4MHz to 40MHz and

generally operates with a crystal frequency 11.0592 MHz.

 Since we know the crystal is pulsing 11,059,000 times per

second and that one machine cycle is 12 pulses. we can
calculate how many instruction cycles the 8051 can execute
per second:
11,059,000 / 12 = 921,583 and 1/ 921,583=1.085µs
MODULE - 2 66
 8051 MACHINE CYCLES
MACHINE CYCLES
 This means that the 8051 can execute 921,583 single-cycle
instructions per second.

 For example, if you are using exclusively 2-cycle instructions

you would find that the 8051 would execute 460,791
instructions per second.

 The 8051 also has two really slow instructions that require a
full 4 cycles to execute-those instructions you’d find
performance to be about 230,395 instructions per second.
MODULE - 2 67
 8051 MACHINE CYCLES
EXAMPLE - 1
 Lets find the time period of the machine cycle in each case for the
following crystal frequency of different 8051 based systems: 11.0592
MHz, 16 MHz, 20 MHz.
Answer:
11.0592 MHz:
11.0592/12 = 921.6 KHz
Machine cycle = 1/921.6 KHz = 1.085us [us=microsecond]
16 MHz:
16MHz/12 = 1.333 MHz
Machine cycle = 1/1.333 MHz = 0.75us [us=microsecond]
20MHz:
20MHz/12 = 1.66 MHz
Machine Cycle = 1/1.66 MHz = 0.60us [us=microsecond]
MODULE - 2 68
 8051 MACHINE CYCLES
EXAMPLE - 2
 Lets find how long it takes to execute each of the following
instructions, for a crystal frequency of 11.0592 MHz. The machine
cycle of a system of 11.0592.z is 1.085 us
INSTRUCTION MACHINE CYCLE TIME TO EXECUTE
MOV R2,#55H 1 1x1.085 us = 1.085 us
DEC R2 1 1x1.085 us = 1.085 us
DJNZ R2,target 2 2x1.085 us = 2.17 us
LJMP 2 2x1.085 us = 2.17 us
SJMP 2 2x1.085 us = 2.17 us
NOP 1 1x1.085 us = 1.085 us
MUL AB 4 4x1.085 us = 4.34 us

MODULE - 2 69
ADDRESSING
MODES

48
 ADDRESSING MODES
 Addressing mode is a way to address an operand. Operand
means the data we are operating upon.

 There are eight addressing modes available in the 8051:

– Immediate
– Direct
– Register
- Register indirect
– Indexed

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 ADDRESSING MODES
IMMEDIATE ADDRESSING MODE
 This addressing mode is named as “immediate” because it
transfers an 8-bit data immediately to the accumulator
(destination operand).

 In general we can write MOV A, #data.

MOV A, #6AH

 The ‘#’ symbol before 6AH indicates that operand is a data

(8 bit). If ‘#’ is not present then the hexadecimal number
would be taken as address.
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 ADDRESSING MODES
IMMEDIATE ADDRESSING MODE

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 ADDRESSING MODES
IMMEDIATE ADDRESSING MODE
 The opcode for MOV A, # data is 74H. The opcode is saved in
program memory at 0202 address. The data 6AH is saved in
program memory 0203.

 When the opcode 74H is read, the next step taken would be to
transfer whatever data at the next program memory address
(here at 0203) to accumulator A (E0H is the address of
accumulator).

 This instruction is of two bytes and is executed in one cycle. So

after the execution of this instruction, program counter will add
2 and move to 0204 of program memory.
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 ADDRESSING MODES
DIRECT ADDRESSING MODE

 Here the address of the data (source data ) is given as

operand. Lets take an example.
MOV A, 04H
 Here 04H is the address of register 4 of register bank#0.
When this instruction is executed, what ever data is stored
in register 04H is moved to accumulator.

 In the figure register 04H holds the data 1FH. So the data
1FH is moved to accumulator.
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 ADDRESSING MODES
DIRECT ADDRESSING MODE

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 ADDRESSING MODES
DIRECT ADDRESSING MODE

 The opcode for instruction MOV A, address is E5H. When

the instruction at 0202 is executed (E5H), accumulator is
made active and ready to receive data.

 Then program control goes to next address that is 0203 and

look up the address of the location (04H) where the source
data (to be transferred to accumulator) is located.

 At 04H the control finds the data 1F and transfers it to

accumulator and hence the execution is completed.
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 ADDRESSING MODES
REGISTER ADDRESSING MODE
 In this addressing mode we use the register name directly
(as source operand). At a time registers can take value from
R0,R1…to R7.An example is shown below.
MOV A, R4
 In register direct addressing mode, data is transferred to
accumulator from the register (based on which register
bank is selected).

 PSW.3 and PSW.4bits are known as register bank select bits

as they are used to select register banks.
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 ADDRESSING MODES
REGISTER ADDRESSING MODE

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 ADDRESSING MODES
REGISTER ADDRESSING MODE

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 ADDRESSING MODES
REGISTER INDIRECT ADDRESSING MODE

 In this addressing mode, address of the data (source data

to transfer) is given in the register operand.
MOV A, @R0

 Here the value inside R0 is considered as an address, which

holds the data to be transferred to accumulator

 If R0 holds the value 20H, and we have a data 2F H stored

at the address 20H, then the value 2FH will get transferred
to accumulator after executing this instruction.
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 ADDRESSING MODES
REGISTER INDIRECT ADDRESSING MODE

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 ADDRESSING MODES
REGISTER INDIRECT ADDRESSING MODE
 The opcode for MOV A, @R0 is E6H. Assuming that register
bank #0 is selected. So the R0 of register bank #0 holds the
data 20H.

 Program control moves to 20H where it locates the data 2FH and
it transfers 2FH to accumulator.

 This is a single byte instruction and the program counter

increments 1 and moves to 0203 of program memory.

 Only R0 and R1 are allowed to form a register indirect

addressing instruction. All register banks are allowed.
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 ADDRESSING MODES
INDEXED ADDRESSING MODE
MOVC A, @A+DPTR and MOVC A, @A+PC
 where DPTR is data pointer and PC is program counter (both are
16 bit registers).

 The source operand is @A+DPTR and we will get the source data
(to transfer) from this location.

 It is nothing but adding contents of DPTR with present content

of accumulator. This addition will result a new data which is
taken as the address of source data (to transfer). The data at
this address is then transferred to accumulator.
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 ADDRESSING MODES
INDEXED ADDRESSING MODE

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 ADDRESSING MODES
INDEXED ADDRESSING MODE

 The opcode for the instruction is 93H. DPTR holds the value
01FE, where 01 is located in DPH (higher 8 bits) and FE is
located in DPL (lower 8 bits).

 Accumulator now has the value 02H. A 16 bit addition is

performed and now 01FE H+02 H results in 0200 H.

 What ever data is in 0200 H will get transferred to accumulator.

The previous value inside accumulator (02H) will get replaced with
new data from 0200H. New data in the accumulator is shown in
dotted line box.
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 ADDRESSING MODES
INDEXED ADDRESSING MODE

 This is a 1 byte instruction with 2 cycles needed for

execution. So, the execution time required for this
instruction is high compared to other addressing modes
(which all were 1 cycle).

 The other example MOVC A, @A+PC works the same way as

above example. The only difference is, instead of adding
DPTR with accumulator, here data inside program counter
(PC) is added with accumulator to obtain the target address.

MODULE - 3 65