Module #01 : Introduction to Verilog HDL

• Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by
integrated circuit (IC) designers. The other one is VHDL.

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• Designs described in HDL are technology-independent, easy to design and debug, and are usually

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more readable than schematics, particularly for large circuits.
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• Verilog is used as an input for synthesis programs which will generate a gate-level description (a

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netlist) for the circuit.

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• The way the code is written will greatly effect the size and speed of the synthesized circuit
• Some Verilog constructs are not synthesizable. (eg. delay)

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• Non-synthesizable constructs should be used only for test benches.

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Note: “Verilog is NOT a Programming Language. It is a Hardware Description Language !!!”

Programming Language : Let the hardware perform a particular function

HDL : Design that Hardware !!

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 Module #01 : Introduction to Verilog HDL
• There are two types of code in most HDLs:

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1) Structural, which is a verbal wiring diagram without storage.
Example 1.1:
assign a=b & c | d;

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assign d = e & (~c);

logic.

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2) Procedural, which is used for circuits with storage, or as a convenient way to write conditional

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Example 1.2:

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always @(posedge clk) // Execute the next statement on every rising clock edge.
count <= count+1;

• if and case statements are only allowed in procedural code. As a result, the synthesizers have been
constructed which can recognize certain styles of procedural code as actually combinational.

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 Module #01 : Introduction to Verilog HDL
Verilog can be used to describe designs at four levels of abstraction:

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(i) Switch level (the switches are MOS transistors inside gates).
(ii) Gate level (interconnected AND, NOR etc.).

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(iii) Register transfer level/Data Flow Level (RTL uses registers connected by Boolean equations).

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(iv) Algorithmic level/Behavioral Level (much like c code with if, case and loop statements).

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 Module #01 : Introduction to Verilog HDL
(i) Switch level (the switches are MOS transistors inside gates).

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Example 1.3:

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module inverter (IN, OUT);

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input IN;
output OUT;
supply0 VSS;

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supply1 VDD;

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pmos p(OUT, VDD, IN);
nmos n (OUT, VSS, IN);
endmodule

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 Module #01 : Introduction to Verilog HDL
(ii) Gate level (interconnected AND, NOR etc.).

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Example 1.4:

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Y1

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module myDesign(A, B, Y); B
input A;
input B;

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output Y; Y2

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and A1(Y1, A,B); B

endmodule
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nand NA1(Y2, A, B);
or O1(Y3, A,B); A

B
Y3

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 Module #01 : Introduction to Verilog HDL
(iii) Register transfer level/Data Flow Level

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Example 1.5:

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module myDesign(A, B, SEL, mux_out); mux_out
input A, B, SEL;
output mux_out;

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assign mux_out = (SEL` & A) + (SEL & B); B 1

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endmodule

SEL

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 Module #01 : Introduction to Verilog HDL
(iv) Algorithmic Level/Behavioral Level

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Design Behavior

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Example 1.6:

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module myDesign(A, B, SEL, mux_out); Verilog Modeling
input A, B, SEL;
output mux_out;

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reg mux_out;

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always @(A, B, SEL)
S I if (SEL = 1) mux_out = B;

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begin
else mux_out = A;
if(SEL)
mux_out = B;
else
mux_out = A;
end

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