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13-Fixed Point Arithmetic Operations - Booths Algorithm-18-01-2024

computer architecture and organisation.

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ayuommishra
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30 views19 pages

13-Fixed Point Arithmetic Operations - Booths Algorithm-18-01-2024

computer architecture and organisation.

Uploaded by

ayuommishra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Computer Architecture and

Organization
• Course Code: BCSE205L
• Course Type: Theory (ETH)
• Slot: D2+TD2
• Timings:

Monday 16:00-16:50
Wednesday 17:00-17:50
Thursday 14:00-14:50

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Syllabus- Module 2
Module:2 Data Representation and Computer Arithmetic 10 hours

Algorithms for fixed point arithmetic operations: Multiplication (Booths,


Modified Booths), Division (restoring and non-restoring) - Algorithms for
floating point arithmetic operations - Representation of nonnumeric data
(character codes).

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Data Representation

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Data Representation: Integer /Fixed point representations
• There are different binary representations for integers
• possible qualifications
1. positive numbers only 2. positive and negative numbers
3. ease of human readability 4. speed of computer operations
• There are 4 commonly known (1 not common) integer representations
1. unsigned
2. sign magnitude
3. one's complement
4. two's complement
All have been used at various times for various reasons

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Fixed point representation of numbers-algorithms
for arithmetic operations

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Addition of
Unsigned Integers

• The sum of 1 and 1 is the 2-bit vector 10, which represents the value 2. We say that the sum
is 0 and the carry-out is 1.
• In order to add multiple-bit numbers, We add bit pairs starting from the low-order (right) end
of the bit vectors, propagating carries toward the high-order (left) end.
a 0011
+b +0 0 0 1
------------------
sum 0 1 0 0
• The carry-out from a bit pair becomes the carry-in to the next bit pair to the left.
• The carry-in must be added to a bit pair in generating the sum and carry-out at that position.
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Unsigned vs. Signed Addition
• Overflows for Unsigned Addition

• Hardware is identical for result bits all between unsigned and signed adder.
• Difference in the is only detection of overflows, that is of results which cannot be represented in
the given format
• Two’s complement addition is extremely Two s similar to unsigned addition

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


2’s Complement Addition
• Just like normal positive binary addition
• You MUST restrict the number of bits
• IGNORE any overflow bits
• maintain bit-size restriction

Example of adding +7 to −3
+7 0111 and
−3 2’s-complement representation for these numbers is 1101
If we perform this addition by adding bit pairs from right to left, we obtain

If we ignore the carry-out from the fourth bit position in this addition, we
obtain the correct answer.
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
2’s Complement Addition: Positive Addition Example
1010 + 210 = 1210

Assuming 2’s complement

000010102 1010
+000000102 + 210
000011002 1210

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


2’s Complement Addition: Negative Addition Example
-1210 + -410 = -1610

111101002 -1210
+111111002 + -410
111100002 -1610

NOTE: We ignored the last overflow bit on the left!

Note: Solve the following


Show the binary addition of -14 + -3 = -17
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
2’s Complement Addition: Subtraction
• To subtract one number (subtrahend) from another (minuend), take the
complement of the subtrahend and add it to the minuend.
• If the numbers are ones (twos) complement numbers, take the ones (twos)
complement of the subtrahend and add it to the minuend.

1610 – 410 = 1610 + -410 = 1210

000100002
+111111002
000011002

NOTE: We ignored the last overflow bit on the left!


Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Overflow / Underflow Problem

• Addition and bit-size restriction allow for possible overflow / underflow


• Overflow
• when the addition of two binary numbers yields a result that is greater than
the maximum possible value
• Underflow
• when the addition/subtraction of two binary numbers yields a result that is
less than the minimum possible value

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Signed Overflow

carry and
carry generated, but no
overflow
overflow

no carry and no overflow


no carry and overflow

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


2’s Complement range: -2n-1 to 2n-1 -1
Overflow Example
• Assume 4-bit restriction and 2’s complement
• Maximum possible value: 24-1 – 1 = 7

610 + 310 = 910

01102 610
+00112 +310
10012 -710  not good!

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


2’s Complement range: -2n-1 to 2n-1 -1
Underflow Example
• Assume 4-bit restriction and 2’s complement
• Minimum possible value: -(24-1) = -8

-510 + -510 = -1010

10112 -510
+10112 +-510
01102 610  not good!

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore


Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

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