Chapter-6: Functional organization

 Implementation of simple data paths

 The data-path is the "brawn" of a processor, since it implements the fetch-decode-execute
cycle.
 The general discipline for data-path design is to:
i. Determine the instruction classes and formats
ii. Design data-path components and interconnections for each instruction class or format, and
iii. Compose the data-path segments designed in Step 2.
 Simple data-path components include memory (stores the current instruction), PC or program
counter (stores the address of current instruction), and ALU (executes current instruction).

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 Implementation of simple data paths
 Load/Store Data-path
 The load/store data-path is illustrated in Figure, and performs the following actions in the order
given:

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 Implementation of simple data paths
1) Register Access takes input from the register file, to implement the
instruction, data, or address fetch step of the fetch-decode-execute cycle.
2) Memory Address Calculation decodes the base address and offset,
combining them to produce the actual memory address.
3) Read/Write from Memory takes data or instructions from the data
memory, and implements the first part of the execute step of the
fetch/decode/execute cycle.
4) Write into Register File puts data or instructions into the data memory,
implementing the second part of the execute step of the
fetch/decode/execute cycle. Prepared by: Elisaye B.@WSU-DTC
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 Control unit: hardwired realization vs. micro programmed
realization
 To execute instructions, the processor must have some means of generating the control
signals needed in the proper sequence.
 Two categories: hardwired control and micro programmed control.
 HARDWIRED CONTROL UNIT ORGANIZATION:
 In the hardwired control, the control unit use fixed logic circuits to interpret instructions
and generate control signals from them.
 An implementation of finite state machine control typically using programmable logic
arrays (PLAs).
 Hardwired control to handle simple instruction.
 The following diagram shows the fixed logic circuit block includes combinational
circuit that generate the required control outputs for decoding and encoding functions.
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HARDWIRED CONTROL UNIT ORGANIZATION:

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 MICROPROGRAMMED CONTROL
 Control signals are generated by a program similar to
machine language programs.
 Microprogramming is a method of control unit design in
which the control signal selection and sequencing
information is stored in ROM or RAM called control
memory (CM).
 The control signal to be activated at any time or specified
by a micro instruction, which is fetched from CM in much
similar way an instruction fetched from main memory.
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 Comparison between Hardwired and Micro programmed Control
Attribute Hardwired Control Microprogrammed
Control
Speed Fast Slow
Control functions Implemented in hardware Implemented in software
Flexibility Not flexible to More flexible, to
accommodate new system accommodate new system
specifications or new specification or new instructions
instructions redesign is required

Ability to handle Difficult Easier

large/complex instruction sets

Ability to support Very difficult Easy

operating systems and
diagnostic features
Design process Complicated Orderly and systematic
Applications Mostly RISC Mainframes, some
Microprocessors microprocessors
Instructionset size Usually under 100 Usually over 100
Instructions instructions
ROM size - 2K to 10K by 20-400 bit
microinstructions
Chip area efficiency Uses least area Uses more area
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 Instruction pipelining
 Pipelining is a particularly effective way of organizing concurrent activity in a computer
system.
 It is a technique of overlapping the execution of successive instructions. This technique
improves performance.
 Consider the instruction:

Add R1, R2, R3

 The above instruction adds the contents of registers R1 and R2, and places the sum to R3.
 The contents of R1 and R2 are first transferred to the inputs of the ALU.
 After addition is performed the result is transferred to register R3 from the processor.
 Here processor can read the next instruction to be executed while performing addition
operation of the current instruction and while transferring the result of addition to ALU, the
operands required for the next instruction can be transferred to the processor.
 This process of overlapping the instruction execution is called Pipelining.
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 Instruction pipelining
 Now consider a computer that has two separate hardware units,

1. Fetching instructions and

2. Executing instructions.
Hardware Organization:
 Sequential Execution:

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 Instruction pipelining
 Basic idea of instruction pipelining:

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 Instruction pipelining
 Basic idea of instruction pipelining:
 The computer is controlled by a clock whose period is such that the fetch and
execute steps of any instruction can each be completed in one clock cycle.
 In the first clock cycle, the fetch unit fetches an instruction I1 (step F1) and
stores it in buffer B1 at the end of the clock cycle.
 In the second clock cycle, the instruction fetch unit proceeds with the fetch
operation for instruction I2 (step F2). Meanwhile, the execution unit performs
the operation specified by instruction I1, which is available to it in buffer B1
(step E1).
 By the end of the second clock cycle, the execution of instruction I1 is
completed and instruction I2 is available. Instruction I2 is stored in B1, replacing
I1, which is no longer needed. Step E2 is performed by the execution unit during
the third clock cycle, while instruction I3 is being fetched byPrepared
the by:fetch unit.
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 Introduction to instruction-level parallelism (ILP)
 Instruction-level parallelism (ILP) is a measure of how many of the operations in a
computer program can be performed simultaneously.
 Pipelining exploits the potential parallelism among instructions.
 This parallelism is called instruction-level parallelism (ILP).
 There are two primary methods for increasing the potential amount of instruction-level
parallelism.
 The first method is
 Increasing the depth of the pipeline to overlap more instructions.
 The amount of parallelism being exploited is higher, since there are more operations
being overlapped. Performance is potentially greater since the clock cycle can be shorter.
 Second approach is
 To replicate the internal components of the computer so that it can launch multiple
instructions in every pipeline stage.
 The general name for this technique is multiple issue. Prepared by: Elisaye B.@WSU-DTC
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 Introduction to instruction-level parallelism (ILP)
 There are two approaches to instruction level parallelism:
 Hardware and Software
 Hardware level works upon dynamic parallelism whereas, the
software level works on static parallelism.
 Static Parallelism An approach to implementing a multiple-issue
processor where many decisions are made by the compiler before
execution.
 Dynamic Parallelism An approach to implementing a multiple-issue
processor where many decisions are made during execution by the
processor.
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Introduction to instruction-level parallelism (ILP)

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