Finite State Machine

ITSC-7698 FPGA-FSM

By Dr.Vittapu
Definition of a State Machine
• All programmable logic designs can be
specified in Boolean form.
• However some designs are easier to
conceptualize and implement using non-
Boolean models.
• The State Machine model is one such model.

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Definition of a State Machine
• A state machine represents a system as a set of
states, the transitions between them, along with
the associated inputs and outputs.
• So, a state machine is a particular
conceptualization of a particular sequential
circuit.
• State machines can be used for many other
things beyond logic design and computer
architecture.

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Finite State Machines
• Any Circuit with Memory Is a Finite State
Machine
• Even computers can be viewed as huge FSMs
• Design of FSMs Involves
• Defining states
• Defining transitions between states
• Optimization / minimization
• Above Approach Is Practical for Small FSMs
Only

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State Machines: Definition of Terms
•State Diagram •Branch
•Illustrates the form and function •A change from present state to
of a state machine. Usually next state.
drawn as a bubble-and-arrow •Mealy Machine
diagram. •A state machine that determines
•State its outputs from the present state
•A uniquely identifiable set of and from the inputs.
values measured at various points •Moore Machine
in a digital system. •A state machine that determines
•Next State its outputs from the present state
•The state to which the state only.
machine makes the next
transition, determined by the
inputs present when the device is
clocked.

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 Finite State Machines
• Finite State Machines (FSMs) are a useful abstraction for
sequential circuits design
• At each clock edge, combinational logic computes outputs
and
next state as a function of inputs and present state

inputs Combinational outputs

+ Logic +
present next
state state

n n

Q D
Registers
CLK
 FSMs: What are they?
• A method of modeling a system comprised of a
limited number of modes of operation. Depending on
which mode it is in the machine will behave in one
manner or another.
• Abstraction tool ( an approach to solving more
complex problems).
• An abstract machine that can be in exactly one of a
finite number of states at any given time.
• The FSM can change from one state to another in
response to some external inputs. The change from
one state to another is called a transition.
Simple Design procedure
Word Description

State transition Diagrams

State encoding

Next State & output Tables

State & output function

realization
 Two Types of FSMs
Moore and Mealy FSMs : different output generation
• Moore FSM:
next
state
S+
inputs D Q outputs
Comb. Comb.
x0...xn Logic
n Registers yk = fk(S)
CLK Logic
n

present state S

• Mealy FSM:
direct combinational path! outputs
yk = fk(S, x0...xn)
inputs S+ Comb.
x0...xn Comb.
n
D
Registers
Q
Logic Logic
CLK
n
S
Present State and Next State

State 4 For any given state, there is a finite

number of possible next states. On
each clock cycle, the state machine
branches to the next state. One of
the possible next states becomes the
new present state, depending on the
State 5 inputs present on the clock cycle.

State 6 State 7

• On a well-drawn state diagram, all possible transitions will be visible,

including loops back to the same state. From this diagram it can be deduced
that if the present state is State 5, then the previous state was either State 4 or
5 and the next state must be either 5, 6, or 7.

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Moore and Mealy Machines
• Both these machine types follow the basic characteristics of
state machines, but differ in the way that outputs are produced.
• Moore Machine:
• Outputs are independent of the inputs, ie outputs are
effectively produced from within the state of the state
machine.
• Mealy Machine:
• Outputs can be determined by the present state alone, or by
the present state and the present inputs, ie outputs are
produced as the machine makes a transition from one state to
another.

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Machine Models

Inputs Inputs

Combinatorial Combinatorial
Logic to Logic to
Determine State Determine State

Present State Present State

Register Bank Register Bank

Combinatorial
Combinatorial
Logic to
Logic to
Determine
Determine
Output Based on:
Output Based on:
 Present State
 Present State
 Present Inputs
Moore Machine Mealy Machine
Output Output
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Moore Machine Diagrams

The Moore State Machine

output is shown inside the
state bubble, because the
output remains the same as State 1
long as the state machine a,b
q,r
remains in that state.
The output can be arbitrarily Input condition that
complex but must be the must exist in order
same every time the i,j to execute these
machine enters that transitions from
state. State 1
Output condition that State 2
results from being in
a particular present x,y
state

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Mealy Machine Diagrams

The Mealy State Machine generates

outputs based on:
 The Present State, and
 The Inputs to the M/c.
So, it is capable of generating many
different patterns of output signals a,b
State 1 q,r
for the same state, depending on the
inputs present on the clock cycle.
Outputs are shown on transitions Input condition that
since they are determined in the i,j must exist in order
same way as is the next state. x,y to execute these
transitions from
State 1
Output condition that
results from being in State 2
a particular present
state

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Moore Machine
• Describe Outputs as Concurrent Statements
Depending on State Only

transition
condition 1

state 1 / state 2 /
output 1 output 2
transition
condition 2

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Mealy Machine
• Describe Outputs as Concurrent Statements
Depending on State and Inputs

transition condition 1 /
output 1

state 1 state 2
transition condition 2 /
output 2

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Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs Can Be Functionally
Equivalent
• Mealy FSM Has Richer Description and
Usually Requires Smaller Number of States
• Smaller circuit area

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Moore vs. Mealy FSM (2)
• Mealy FSM Computes Outputs as soon as
Inputs Change
• Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM
• Moore FSM Has No Combinational Path
Between Inputs and Outputs
• Moore FSM is less likely to have a shorter critical
path

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 Moore FSM - Example 1
• Moore FSM that Recognizes Sequence 10
0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset
0
S0: No S1: “1” S1: “10”
Meaning elements observed observed
of states: of the
sequence
observed

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Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence 10
0/0 1/0 1/0

S0 S1

reset 0/1
S0: No S1: “1”
Meaning elements observed
of states: of the
sequence
observed

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Moore & Mealy FSMs – Example 1

clock
0 1 0 0 0
input

S0 S1 S2 S0 S0
Moore
S0 S1 S0 S0 S0
Mealy

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 Finite State Machine (FSM)
0
00/0
1 0
01/0 0
0 1
11/0 =O‫פלט‬
1
10/1
1
• Moore FSM

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 Finite State Machine (FSM)
0/0
00
1/0 0/0
01 0/0
0/0 1/0
10 ‫פלט‬
1/1
11
1/1

• Mealy FSM

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 0
00/0
I=0 I=1
1 0
At Bt At+1 Bt+1 At+1 Bt+1 Ot
01/0
1
0 0 0 0 0 1 0
0 0 1 0 0 1 1 0
11/0
1 1 1 0 0 1 0 0
0
1 0 0 0 1 0 1
10/1
1

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 X=0 X=1 X=0 X=1
At Bt At+1 Bt+1 At+1 Bt+1 Ot Ot
0 0 0 0 0 1 0 0
0 1 0 0 1 0 0 0
1 0 0 0 1 1 0 1
1 1 0 0 1 1 0 1

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 0
00/0
I=0 I=1
1 0
At Bt At+1 Bt+1 At+1 Bt+1 Ot
01/0
0 0 0 0 0 1 0
1
0 1 0 0 1 1 0
11/0
1 0 1 1 0 0 1 0 0
0
1 0 0 0 1 0 1
10/1
1
AB AB

10 11 01 00 Bt+1 10 11 01 00 At+1
0 0
I
1 1
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I
D Q
A
Q’
O
D Q
B
Q’

At+1= A*I + B * I= I(A+B)

Bt+1= A*I
O = A*B

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 D Q
A
Q’

X Out
D Q
B
Q’

• QA, QB ‫ו‬- X.

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 Mealy Vs Moore
• They differ only in how the output function is computed
• Moore: Output values are a function of the state only
• Mealy: Output Values are generated based on both the state
of the circuit and the present values of its inputs.
• Both are considered to have similar computation
capability, although Mealy machine normally
accomplishes the same task with fewer states.
• But, when the FSM is used as a control circuit, Moore
approach provides safer control signal timing.
 Moore vs. Mealy FSMs

Consider a snail that crawls down

a paper tape with 1’s and 0’s on
it. The snail smiles whenever the
last four digits it has crawled
over are 1101.
• Design Moore and Mealy FSMs
of the snail’s brain.
• Write Verilog code for your
Moore and Mealy FSMS.
State Transition Diagrams: Looking for
“1101” 01 0 1

1 S1 1 S2 0 S3 1 S4
S 0 0 0 1
0 0
0 0

Moore Machine: States indicate output

1/1
0/0
0/0
1/0
1/0 1/0 0/0
S0 S1 S2 S3

0/0

Mealy Machine: Arcs indicate input/output

 Moore Machine
Next State Output
S A S’ S Y

S0 0 S0 S0 0
S0 1 S1 S1 0
S1 0 S0 S2 0
S1 1 S2 S3 0
S2 0 S3 S4 1
S2 1 S2
S3 0 S0
S3 1 S4
S4 0 S0
S4 1 S2
Moore Machine
A

S ‘2 S2
Y

Next State Output CLK

S A S’ S Y

000 0 000 000 0 S ‘1 S1

000 1 001 001 0
CLK
001 0 000 010 0
001 1 010 011 0
010 0 011 100 1
010 1 010
011 0 000 S ‘0 S0
011 1 100
CLK
100 0 000
100 1 010
 Mealy Machine

S A S’ Y
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S3 0
S2 1 S2 0
S3 0 S0 0
S3 1 S1 1
 Mealy Machine A

S ‘1 S1
S A S’ Y
CLK
00 0 00 0
00 1 01 0
01 0 00 0
01 1 10 0 S ‘0 S0

10 0 11 0 CLK
10 1 10 0
11 0 00 0
11 1 01 1 Y
More Intuitive Solutions using Shift Registers

CLK

Mealy Form: Output Depends on Input Immediately

CLK

Moore Form: Output Depends Only on State

 Exercise

Consider a snail that crawls down

a paper tape with 1’s and 0’s on
it. The snail smiles whenever it
detects two consecative ones.
• Design Moore and Mealy FSMs
of the snail’s brain.
• Write Verilog code for your
Moore and Mealy FSMS.
Exercise: Detect consicative 1’s
Moor Verilog FSM: Detect consicative 1’s
 FSM Issues

 1. Power on Reset
 2. The clock Frequency
 Then we started which some issues and the finite state machine are the controller.
 We have looked at how to bring the state machine to a starting state using a reset very simple
thing.
 So, you should not forget to bring the state machine it was starting state by you know putting the
reset,
 second thing we have looked at is what is the kind of most appropriate clock frequency for a
controller for a state machine.
 We have looked at the maximum frequency but then that is not a good idea to run the state machine has the maximum
frequency it dissipate lot of power, suppose the data path is running at a much lower frequency.
 So, what should be the kind of how much you can bring down the clock frequency of the state machine
o So, this is the slide on power on reset. So, this is the state machine you know
kind of structure.
o You have the flip-flops which gives the present state, and that combine with the
input will, you know give the next state using next state logic.
o The present state is decoded to produce the outputs, some time, some output
maybe just a function of present state, and some output could be a function of
the present state and input.
2. Clock frequency issue

 There are the clock period we use a maximum time delay and for
the hold old time violation.
 We use the minimum delays okay, because it is the hold time
violation happens with the same edge.
 the maximum clock frequency. But then we set there is no kind
of point in clocking at the maximum clock frequency, because it
dissipates lot of power and more over.