Chap.

12 Memory Organization 12-1

 12-1 Memory Hierarchy

 Memory hierarchy in a computer system : Fig. 12-1
 Main Memory : memory unit that communicates directly with the CPU (RAM)
 Auxiliary Memory : device that provide backup storage (Disk Drives)
 Cache Memory : special very-high-speed memory to increase the processing
speed (Cache RAM)
Auxiliary memory
Magnetic
tapes
Main
I/O processor
memory
Magnetic
disks

Cache
CPU
memory

 Multiprogramming
 enable the CPU to process a number of independent program concurrently

 Memory Management System : sec. 12-7

 supervise the flow of information between auxiliary memory and main memory

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 12-2 Main Memory

 Bootstrap Loader
 A program whose function is to start the computer software operating when power
is turned on P ow er-O N

 RAM and ROM Chips

FFFF:0000
 Typical RAM chip : Fig. 12-2 (R eset P oint)

» 128 X 8 RAM : 27 = 128 (7 bit address lines) P O ST

Bootstrap Loader
 Typical ROM chip : Fig. 12-3 System Init. Bootstrap ROM
» 512 X 8 ROM : 29 = 512 (9 bit address lines) Boot ROM
IN T 19
Chip select 1 CS1
Load Bootstrap R ecord
Chip select 2 CS2 (Track 0, Sector 0)
128×8
Read RD 8 bit data bus
RAM
Load O perating System
W rite WR (IO .SYS, M SD O S.SYS, C O M M AN D .C O M )
7 bit address AD7

(a) Block diagram Chip select 1 CS1

CS1 CS2 RD W R Memory function State of data bus Chip select 2 CS2
0 0 × × Inhibit High-impedance
512×8
8 bit data bus
0 1 × × Inhibit High-impedance ROM
1 0 0 0 Inhibit High-impedance
1 0 0 1 W rite Input data to RAM
1 0 1 × Read Output data from RAM 9 bit address AD9
1 1 × × Inhibit High-impedance

(b) Function table

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 Memory Address Map

 Memory Configuration : 512 bytes RAM + 512 bytes ROM
» 1 x 512 byte ROM + 4 x 128 bytes RAM
 Memory Address Map : Tab. 12-1 Address bus CPU

16 - 11 10 9 8 7 - 1 RD W R Data bus

» Address line 9 8
Decoder
 RAM 1 0 0 : 0000 - 007F 3 2 1 0
CS1

 RAM 1 0 1 : 0080 - 00FF CS2

RD
128×8 Data
RAM 1
 RAM 1 1 0 : 0100 - 017F WR
AD7

 RAM 1 1 1 : 0180 - 01FF CS1

» Address line 10 CS2

RD
128×8
RAM 2
Data

ROM 1 : 0200 - 03FF

WR

AD7

 Memory Connection to CPU : Fig. 12-4 CS1

CS2

» 2 x 4 Decoder : RAM select (CS1)

128×8 Data
RD
RAM 3
WR
AD7
» Address line 10
CS1
 RAM select : CS2 CS2
128×8 Data
RD
RAM 4
 ROM select : CS2 의 Invert WR
AD7

» 참고 CS1

 RD : ROM 의 CS1 은 보통 1-7

CS2
128×8 Data
ROM
8
OE(Output Enable) 로 사용 9
AD9

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Tracks
 12-3 Auxiliary Memory
 Magnetic Disk : Fig. 12-5, FDD, HDD

to r
 Magnetic Tape : Backup or Program 저장

S ec
 Optical Disk : CDR, ODD, DVD text

 12-4 Associative Memory

 Content Addressable Memory (CAM)
 A memory unit accessed by content Read/W rite
head

 Block Diagram : Fig. 12-6

Argum ent register (A)

이름 주소
Key register (K)

A Register 101 111100 Argument

M atch
K Register 111 000000 Key (Mask) register

Memory 내용 Input

Word 1 100 111100 M = 0 Associative m em ory

array and logic M

Word 2 101 000011 M = 1 Match Logic

Read
m words
W rite
n bits per word

M = 1 일때 출력 Output

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 m word x n cells per word : Fig. 12-7

A i K j

Input
A1 A j An

W rite
K1 K j Kn

W ord 1 C 11 C 1j C 1n M1 R S Match
To M i
F ij logic
Read
W ord i C i1 C ij C in Mi

W ord m C m1 C mj C mn Mm

Bit 1 Bit j Bit n

Output

 Match Logic
 One cell of associative memory : Fig. 12-8
» Input = 1 or 0 에 따라 Write 신호와 동시에 F/F 에 저장
» A 와 K 에 의해 Match Logic 에서 M=1 이면 (M 을 READ 에 직접 연결 가능함 )
» Read 신호에 따라 F/F 에서 데이터를 읽는다

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 Match Logic : Fig. 12-9 K1 A1 K2 A2 Kn An

» Aj = Argument, Fij = Cell ij 번째 bit F'i1 F i1 F'i2 F i2 F'in F in

» j 번째 1 bit match 조건
xj = Aj Fij (1 AND 1)+ Aj’ Fij’ (0 AND 0)
» 1 - n 까지 n bits match 조건 Mi = x1x2…..xn
» Key bit Kj : xj + Kj’
 Kj = 0 : Aj 와 Fij 는 no comparison ( Kj : xj + 1 = 1 )
 Kj = 1 : Aj 와 Fij 는 comparison ( Kj : xj + 0 = xj )
» Match Logic for word I : Mi

Mi = (x1 + K1’) (x2 + K2’)…. (xn + Kn’)

n

j 1

=  (xj + Kj’)
n

j 1

= (Aj Fij + Aj’ Fij’ + Kj’)

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 12-5 Cache Memory

 Locality of Reference
 the references to memory tend to be confined within a few localized areas in
memory
 Cache Memory : a fast small memory
 keeping the most frequently accessed instructions and data in the fast cache
memory
 Cache 의 설계 요소
 cache size : 보통 256 K byte ( 최대 512 K byte)
 mapping method : 1) associative, 2) direct, 3) set-associative
 replace algorithm : 1) LRU, 2) LFU, 3) FIFO
 write policy : 1) write-through, 2) write-back

 Hit Ratio
 the ratio of the number of hits divided by the total CPU references (hits + misses)
to memory
» hit : the CPU finds the word in the cache ( 보통 0.9 이상 )
» miss : the word is not found in cache (CPU must read main memory)
 예제 : cache memory access time = 100 ns, main memory access time = 1000
총 10 회 ns, hit ratio = 0.9
Memory 참조
» 1 회 miss : 1 x 1000 ns Cache 가 없으면 1000 ns,
1900 ns / 10 회 = 190 ns 따라서 약 5 배 성능 향상
» 9 회 hit : 9 x 100 ns
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 Mapping
 The transformation of data from main memory to cache memory
» 1) Associative mapping
» 2) Direct mapping
» 3) Set-associative mapping
 Example of cache memory : Fig. 12-10
main memory : 32 K x 12 bit word (15 bit address lines)
cache memory : 512 x 12 bit word Main memory
32K×12 Cache memory
CPU

» CPU sends a 15-bit address to cache 512×12

 Hit : CPU accepts the 12-bit data from cache

 Miss : CPU reads the data from main memory (then data is written to cache)
 Associative mapping : Fig. 12-11 Cache Coherence (Sec. 13-5)
 Cache memory 로 고가의 associative memory 사용 CPU address(15 bits)

 Address 와 Data 가 직접 Cache memory 에 사용됨 Argument register

 Direct mapping : Fig. 12-12 Address D ata

0 1 0 0 0 3 4 5 0
 Cache memory 로 저가의 일반 memory 사용 0 2 7 7 7 6 7 1 0

 Tag field (n - k) 와 Index field (k) 를 사용 2 2 3 4 5 1 2 3 4

» 2k words cache memory + 2n words main memory

 Tag = 6 bit (15 - 9), Index = 9 bit

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6 bits 9 bits
Tag Index

Tag (6 bit)
00 - 63
00 000 000
512×12
32K×12
Cache memory
Index (9 bit) Octal
Hex Main memory address
000 - 511 Address
Address = 9 bits
Data = 12 bits
1FF
Address = 15 bits
3F 1FF Data = 12 bits

Memory Index
address Memory data address Tag Data
 Direct mapping cache organization : Fig. 12-13 000000 1 2 2 0 000 00 1 2 2 0

» 예제 : 02000 번지를 읽는 경우 00777 2 3 4 0

 1) 우선 Index 000 을 cache 에서 찾는다 01000 3 4 5 0
 2) 다음은 Tag 를 cache 에서 비교한다
 3) 000 Index 에 있는 cache tag 는 00 이다
01777 4 5 6 0 777 02 6 7 1 0
(02 가 아니다 )
02000 5 6 7 0
 4) 따라서 miss (b) Cache memory
 5) 그러므로 main memory 에서 data read
(address 02000 = 5670 read) 02777 6 7 1 0

(a) Main memory

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 Direct mapping cache with block size of 8 words : Fig. 12-14

» 64 block x 8 word = 512 cache words size
 8 word 를 1 개의 block 단위로 update

Index Tag Data 6 6 3

Index Tag Data Tag Data
000 01 3450 Tag Block Word
Block 0 000 0 1 3 4 5 0 0 2 5 6 7 0
007 01 6578
Index
010
Block 1
017

770 02
Block 63 777 0 2 6 7 1 0 0 0 2 3 4 0
777 02 6710

 Set-associative mapping : Fig. 12-15 (two-way)

 Direct mapping ( Fig. 12-13(b)) 에서 같은 Index 에 다른 tag 를 자주 읽으면
속도가 저하됨 ( 예제 02777, 01777 )
 따라서 set 의 개수를 증가시키면 속도가 향상된다 .

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 Replacement Algorithm : cache miss or full 일때

 1) LRU (Least Recently Used) : 최근에 가장 적게 사용된 block 교체
 2) LFU (Least Frequently Used) : 사용 빈도가 가장 적은 block 교체
 3) FIFO (First-In First-Out) : 가장 오래된 block 교체

 Writing to Cache : Cache Coherence(Sec. 13-5) Cache READ 는 문제 없음

 Cache 에 있는 내용이 변경된 (WRITE) 경우 , Cache 의 block 이 교체되기 전에
main memory 에 내용도 update 해야 함
Main memory 와 Cache memory 의 내용이 동일해야 함 : 통일성 ( 일관성 ) 유지

» 1) Write-through : Cache write 와 동시에 main memory 도 항상 동시에 write 한다 .

» 2) Write-back : Cache write 시에 내용이 변경되었다는 flag 만 set 해 놓고 나중에
block 이 교체되기 전에 flag 를 검사하여 변경된 부분만 나중에 write 한다 .
 따라서 Write-back 방식은 main memory 가 무효한 상태에 빠져 있을 수 있다 .

 Cache Initialization
 Cache is initialized : 이때 cache 는 empty 상태이고 invalid data 를 갖을 수 있다 .
» 1) when power is applied to the computer
» 2) when main memory is loaded with a complete set of programs from auxiliary
memory
 valid bit
» indicate whether or not the word contains valid data
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 12-6 Virtual Memory

 Virtual Memory : Auxiliary memory Main memory
 Translate program-generated (Aux. Memory) address into main memory location
» Give programmers the illusion that they have a very large memory, even though the
computer actually has a relatively small main memory
 예제 : Intel Pentium Processor
» Physical Address Lines = A0 - A31 : 232 = 230 X 22 = 4 Giga
» Logical Address = 46 bits address : 2 46 = 240 X 26 = 64 Tera
 Address Space & Memory Space
 Address Space : Virtual Address Auxiliary m em ory

» Address used by a programmer Main m em ory

 Memory Space : Physical Address(Location) Program 1

Program 1
» Address in main memory Data 1,1
Data 1,2
 예제 : Fig. 12-16
Data 1,1
 address space (N) = 1024 K = 220 Program 2

» Auxiliary Memory Data 2,1

Mem ory space
 M = 32K = 2 15
memory space (M) = 32 K = 2 15
Address space
» main Memory N = 1024K = 2 20

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 Memory table for mapping a virtual address : Fig. 12-17

 Translate the 20 bits Virtual address into the 15 bits Physical address
Virtual address

Virtual M ain m em ory

address M em ory address M ain
register m aping register m em ory
(20 bits) table (15 bits)

M em ory table M ain m em ory

buffer register buffer register

 Address Mapping Using Pages : Fig. 12-18 Page 0

Page 1
 Address mapping 을 간단하게 하기 위하여 사용
Page 2
» Address space 와 memory space 를 fixed size 로 Page 3
Page 4 Block 0
분할하여 사용함
Page 5 Block 1
 Address space : 1 K page 로 분할
Page 6 Block 2
 Memory space : 1 k block 으로 분할
Page 7 Block 3
» Address space 의 4 개 page 가 memory space 에
Address space Mem ory space
block 에 들어 갈수 있다 . N = 8K = 2 13 M = 4K = 2 12

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 Memory table in a paged system : Fig. 12-19

Page no.
Line number
1 0 1 0 1 0 1 0 1 0 0 1 1 Virtual address

Table Presence
address bit
000 0 Main memory
001 11 1 Block 0
010 00 1 Block 1
011 0
1 01 0101010011 Block 2
100 0 Main memory Block 3
101 01 1 address register
110 10 1
MBR
111 0
1

01 1

Memory page table

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 Associative memory page table : Fig. 12-20

 Associative memory 를 이용하여 block number(01) 를 곧바로 찾는다

Virtual m em ory

Page no.

1 0 1 Line num ber Argum ent register

1 1 1 0 0 Key register

0 0 1 1 1
0 1 0 0 0
Associative m em ory
1 0 1 0 1
1 1 0 1 0

Page no. Block no.

 Page(Block) Replacement
 Page Fault : the page referenced by the CPU is not in main memory
» a new page should be transferred from auxiliary memory to main memory
 Replacement algorithm : FIFO 와 LRU 주로 사용

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 12-7 Memory Management Hardware

 Basic components of a Memory Management Unit
 1) Address mapping
 2) Common program sharing
 3) Program protection

 MMU : OS 에서 지원 해야 함
 1) CPU 에 내장된 형태
 2) 별도의 memory controller 형태
 Segment
 A set of logically related instruction or data elements associated with a given
name
 예제 : a subroutine, an array of data, a table of symbol, user’s program

 Logical Address
 the address generated by a segmented program
 similar to virtual address
» Virtual Address : fixed-length page
» Logical Address : variable-length segment

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 Segmented-page MMU
 Fig. 12-21(a) : 2 개의 table(segment, page) 을 사용함
» 따라서 2 개의 table 을 읽는데 많은 시간이 소모됨
 Fig. 12-21(b) : Associative memory 를 이용한 1 개의 table 을 사용함
» 따라서 속도가 빠르다
» TLB (Translation Look-a-side Buffer)
 associative memory 를 이용한 most recently reference table
 Numerical Example
 예제 : Logical address & Physical address (Fig. 12-22)
» Logical Address : 4 8 8
 4 bit segment : 16 segments Segment Page W ord
 8 bit page : 256 pages (a) Logical address format : 16 segments of 256 pages each,
 8 bit word : 256 address field each page has 256 words
Address
» Physical Address : or Index
 12 bit block : 4096 blocks 12 8
 8 bit word : 256 address field Block W ord
2 20 × 32
Physical memory

(b) Physical address format : 4096 blocks of 256 word each,

each word has 32 bits

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 예제 : Logical & Physical address assignment (Fig. 12-23)

Logical Address

Hexadecimal Page Table

address Page number
6 00 00
6 00 FF Page 0 Segment Page Block
6 01 00
6 01 FF
Page 1 6 00 012
6 02 00 6 01 000
Page 2
6 02 FF 6 02 019
6 03 00
6 03 FF
Page 3 6 03 053
6 04 00 6 04 A61
Segment 6 04 FF
Page 4

Page (a) Logical address assignment (b) Segment-page versus

Word memory block assignment

Block number 019 를 찾는다

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Logical address
Logical address (in haxadecim al)
Segment Page W ord 6 02 7E

Segment table Physical m emory

Page table
Segment table Page table 000 00
0 00
Block 0
000 FF

6 35
35 012
36 000
+ + 012 00
37 019
Block 12
38 053 012 FF
39 A61
F A3

Block W ord
Physical address 019 00
32 bit word
019 7E
(a) Logical to physical address mapping A3 012 019 FF

(a) Segm ent and page table mapping

Argument register
Segment Page Block
Segment Page Block
6 02 019
6 04 A61

(b) Associative memory translation look-aside buffer (TLB) (b) Associative m emory (TLB)

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 Memory Protection
 Typical segment descriptor : Fig. 12-25

segment Length
Base address Length Protection
Base address

 Access Rights : protecting the programs residing in memory

» 1) Full read and write privileges : no protection
» 2) Read only : write protection
» 3) Execute only : program protection
» 4) System only : operating system protection

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Address bus CPU

16 - 11 10 9 8 7 - 1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2
128×8 Data
RD
RAM 1
WR
AD7

CS1
CS2
128×8 Data
RD
RAM 2
WR
AD7

CS1
CS2
128×8 Data
RD
RAM 3
WR
AD7

CS1
CS2
128×8 Data
RD
RAM 4
WR
AD7

CS1
CS2
1-7 128×8 Data
ROM
8
AD9
9

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.