VLSI

VLSI Testing
Testing

Lecture
Lecture 10:
10: DFT
DFT and
and Scan
Scan
 Definitions
 Ad-hoc methods
 Scan design
 Design rules
 Scan register
 Scan flip-flops
 Scan test sequences
 Overheads
 Boundary scan
 Summary

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 1
 Definitions
Definitions
 Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
 DFT methods for digital circuits:
 Ad-hoc methods
 Structured methods:
 Scan
 Partial Scan
 Built-in self-test (BIST)
 Boundary scan
 DFT method for mixed-signal circuits:
 Analog test bus

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 2
 Ad-Hoc
Ad-Hoc DFT
DFT Methods
Methods
 Good design practices learnt through experience are used as
guidelines:
 Avoid asynchronous (unclocked) feedback.
 Make flip-flops initializable.
 Avoid redundant gates. Avoid large fanin gates.
 Provide test control for difficult-to-control signals.
 Avoid gated clocks.
 Consider ATE requirements (tristates, etc.)
 Design reviews conducted by experts or design auditing tools.
 Disadvantages of ad-hoc DFT methods:
 Experts and tools not always available.
 Test generation is often manual with no guarantee of high fault
coverage.
 Design iterations may be necessary.

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 3
 Scan
Scan Design
Design
 Circuit is designed using pre-specified design rules.
 Test structure (hardware) is added to the verified
design:
 Add a test control (TC) primary input.
 Replace flip-flops by scan flip-flops (SFF) and connect to form
one or more shift registers in the test mode.
 Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all testable
faults in the combinational logic.
 Add shift register tests and convert ATPG tests into
scan sequences for use in manufacturing test.

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 4
 Scan
Scan Design
Design Rules
Rules

 Use only clocked D-type of flip-flops for all state

variables.
 At least one PI pin must be available for test; more
pins, if available, can be used.
 All clocks must be controlled from PIs.
 Clocks must not feed data inputs of flip-flops.

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 5
Correcting
Correcting a
a Rule
Rule Violation
Violation
 All clocks must be controlled from PIs.

Comb.
logic D1 Q

FF Comb.
D2 logic
CK

Comb.
logic
Q
D1
D2 FF Comb.
logic
CK

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 6
 Scan
Scan Flip-Flop
Flip-Flop (SFF)
(SFF)
D Master latch Slave latch
TC
Logic Q
overhead

MUX
SD Q

CK D flip-flop

CK Master open Slave open

t

TC Normal mode, D selected Scan mode, SD selected

t

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 7
Level-Sensitive
Level-Sensitive Scan-Design
Scan-Design
Flip-Flop
Flip-Flop (LSSD-SFF)
(LSSD-SFF)
Master latch Slave latch
D
Q

MCK Q

SCK D flip-flop

SD

Normal
MCK

mode
Logic TCK
overhead
TCK MCK

mode
Scan
TCK

SCK t
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 8
 Adding
Adding Scan
Scan Structure
Structure
PI PO

Combinational SFF SCANOUT

logic SFF

SFF

TC or TCK Not shown: CK or

MCK/SCK feed all
SCANIN SFFs.
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 9
 Comb.
Comb. Test
Test Vectors
Vectors

PI I1 I2 O1 O2 PO

Combinational
SCANIN
SCANOUT
TC
logic
Next
Present S1 S2 N1 N2 state
state

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 10
 Comb.
Comb. Test
Test Vectors
Vectors
Don’t care
or random
PI I1 I2 bits

SCANIN S1 S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

PO O1 O2

SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 11
 Testing
Testing Scan
Scan Register
Register
 Scan register must be tested prior to application
of scan test sequences.
 A shift sequence 00110011 . . . of length nsff + 4 in
scan mode (TC = 0) produces 00, 01, 11 and 10
transitions in all flip-flops and observes the result
at SCANOUT output.
 Total scan test length: (ncomb
+ 2) nsff + ncomb + 4 clock periods.
 Example: 2,000 scan flip-flops, 500 comb. vectors,
total scan test length ~ 106 clocks.
 Multiple scan registers reduce test length.
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 12
 Multiple
Multiple Scan
Scan Registers
Registers
 Scan flip-flops can be distributed among
any number of shift registers, each having
a separate scanin and scanout pin.
 Test sequence length is determined by the
longest scan shift register.
 Just one test control (TC) pin is essential.
PI/SCANIN PO/
Combinational
M SCANOUT
logic U
SFF X

SFF
SFF

TC

CK
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 13
 Scan
Scan Overheads
Overheads
 IO pins: One pin necessary.
 Area overhead:
 Gate overhead = [4 nsff/(ng+10nff)] x 100%
where ng = comb. gates; nff = flip-flops
Example – ng = 100k gates, nff = 2k flip-flops
overhead = 6.7%.
 More accurate estimate must consider scan wiring
and layout area.
 Performance overhead:
 Multiplexer delay added in combinational path;
approx. two gate-delays.
 Flip-flop output loading due to one additional
fanout; approx. 5 - 6%.
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 14
 Hierarchical
Hierarchical Scan
Scan
 Scan flip-flops are chained within
subnetworks before chaining subnetworks.
 Advantages:
 Automatic scan insertion in netlist
 Circuit hierarchy preserved – helps in
debugging and design changes
 Disadvantage: Non-optimum chip layout.
Scanin Scanout
SFF1 SFF4
SFF1 SFF3
Scanin
Scanout
SFF2 SFF3 SFF4 SFF2

Hierarchical netlist Flat layout

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 15
 Optimum
Optimum Scan
Scan Layout
Layout
X’
X

IO SFF
pad cell

SCANIN
Flip-
flop
cell
Y Y’

TC SCAN
OUT

Routing
channels
Interconnects Active areas: XY and X’Y’

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 16
 Scan
Scan Area
Area Overhead
Overhead
Linear dimensions of active area:
X = (C + S) / r
X’ = (C + S + S) / r y = track dimension, wire
width+separation
Y’ = Y + ry = Y + Y(1--) / T C = total comb. cell width
S = total non-scan FF cell
Area overhead width
X’Y’--XY s = fractional FF cell area
= S/(C+S)
= -------------- x 100%  = SFF cell width fractional
XY increase
1-- r = number of cell rows
or routing channels
= [(1+s)(1+ -------) – 1] x 100%  = routing fraction in active
T area
T = cell height in track
dimension y
1--
= (s + ------- ) x 100%
T
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 17
 Example:
Example: Scan
Scan Layout
Layout
 2,000-gate CMOS chip
 Fractional area under flip-flop cells, s = 0.478
 Scan flip-flop (SFF) cell width increase, = 0.25
 Routing area fraction, = 0.471
 Cell height in routing tracks, T = 10
 Calculated overhead = 17.24%
 Actual measured data:
Scan implementation Area overhead Normalized clock rate
______________________________________________________________________

None 0.0 1.00

Hierarchical 16.93% 0.87

Optimum layout 11.90% 0.91

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 18
 ATPG
ATPG Example:
Example: S5378
S5378
Original Full-scan

Number of combinational gates 2,781 2,781

Number of non-scan flip-flops (10 gates each) 179 0
Number of scan flip-flops (14 gates each) 0 179
Gate overhead 0.0% 15.66%
Number of faults 4,603 4,603
PI/PO for ATPG 35/49 214/228
Fault coverage 70.0% 99.1%
Fault efficiency 70.9% 100.0%
CPU time on SUN Ultra II, 200MHz processor 5,533 s 5s
Number of ATPG vectors 414 585
Scan sequence length 414 105,662

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 19
 Boundary
Boundary Scan
Scan (BS)
(BS)
IEEE
IEEE 1149.1
1149.1 Standard
Standard
 Developed for testing chips on a printed circuit
board (PCB).
 A chip with BS can be accessed for test from the
edge connector of PCB.
 BS hardware added to chip:
 Test Access port (TAP) added
 Four test pins
 A test controller FSM
 A scan flip-flop added to each I/O pin.
 Standard is also known as JTAG (Joint Test
Action Group) standard.

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 20
 Boundary
Boundary Scan
Scan Test
Test Logic
Logic

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 21
 Summary
Summary
 Scan is the most popular DFT technique:
 Rule-based design
 Automated DFT hardware insertion
 Combinational ATPG
 Advantages:
 Design automation
 High fault coverage; helpful in diagnosis
 Hierarchical – scan-testable modules are easily combined
into large scan-testable systems
 Moderate area (~10%) and speed (~5%) overheads
 Disadvantages:
 Large test data volume and long test time
 Basically a slow speed (DC) test
 Variations of scan:
 Partial scan
 Random access scan (RAS)
 Boundary scan (BS)
Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 22
 Problems
Problems to
to Solve
Solve
 What is the main advantage of scan method?

 Given that the critical path delay of a circuit is 800ps and

the scan multiplexer adds a delay of 200ps, determine the
performance penalty of scan as percentage reduction in the
clock frequency. Assume 20% margin for the clock period
and no delay due to the extra fanout of flip-flop outputs.

 How will you reduce the test time of a scan circuit by a

factor of 10?

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 23
 Solutions
Solutions
 What is the main advantage of scan method?
Only combinational ATPG (with lower complexity) is used.

 Given that the critical path delay of a circuit is 800ps and the scan
multiplexer adds a delay of 200ps, determine the performance penalty
of scan as percentage reduction in the clock frequency. Assume 20%
margin for the clock period and no delay due to the extra fanout of flip-
flop outputs.
Clock period of pre-scan circuit = 800+160 = 960ps
Clock period for scan circuit = 800+200+200 = 1200ps
Clock frequency reduction = 100×(1200-960)/1200 = 20%

 How will you reduce the test time of a scan circuit by a factor of 10?
Form 10 scan registers, each having 1/10th the length of a single scan
register.

Copyright 2001, Agrawal & Bushnell Lecture 10: DFT and Scan 24