Interfacing and data

Transfer Techniques

Presented by:
Dishant Khosla
Asst. Professor
Modes of I/O data transfer
Programmed I/O

Interrupt Initiated I/O

Direct Memory Access

 Programmed Input/Output
• It involves two operations:
Transfer of data from I/O devices to the CPU registers
Transfer of data from CPU registers to I/O devices
In this CPU is responsible for all communication with I/O devices and
for extracting the information from the main memory for output and
storing data in main memory for input.
Data transfer from I/O device to CPU
Drawbacks of Programmed I/O
• It is very time consuming because CPU wastes lot of time checking
and verifying the status of an I/O device.
• It is very slow and suitable for character transmission I/O devices such
as printers, keyboards and monitors.
• This is inefficient in terms of CPU usage.
Interrupt Initiated I/O
• This method is better than Programmed I/O because CPU need not to
check out the devices that want to transfer the data.
• It saves a lot of time.
• It is more efficient
Working of interrupt initiated I/O
Direct Memory Access(DMA)

• The ability of an I/O subsystem to transfer data to and from a memory

subsystem without processor intervention
• DMA controller takes over control of the subsystem bus from the CPU
and like CPU it generates address, data and control signals to transfer
between memory and I/O devices.
• It is commonly used for high speed data transfer.
Two control signals are used to request & acknowledge a DMA transfer in the microprocessor based
system i.e HOLD and HLDA signal

DMA Controller operation

Transfer Modes
DMA controller uses three methods for data transfer:
Burst Transfer: Block of memory words is transferred continuously
between main memory and peripheral device. It is fastest DMA transfer.
In this mode, DMA controller sends ‘HOLD’ signal to the microprocessor
and waits for ‘HLDA’ signal. After receiving HLDA signal, the DMA
controller gains control of the system bus and execute cycle to transfer
one byte. After transferring one byte ,it increments memory address
and decrements counter and transfers next byte. After transferring all
bytes, DMA disable HOLD signal and enters into slave mode.
Cycle Stealing: Transfer one byte of data at a time. After
transfer of one byte of data, DMA controller handover the
system buses back to the CPU. This type of DMA is slower
than burst DMA.
DMA controller steals out one clock cycle rapidly after
sometime for data transfer between main memory and
peripheral.
After transfer one byte, it enters into slave mode.

Transparent mode: DMA controller only transmits data

when CPU doesn’t need the system buses. This is called
hidden DMA transfer mode.
Mapping
• 8085 has capability of 8 bit I/O address so it can address 255 I/O
ports.
• It provides facility to treat I/O devices as memory location.
• In this, One can map I/O devices in memory map.
• Two technquies of I/O mapping:
 I/O mapped I/O scheme
Memory mapped I/O scheme
I/O Mapped I/O scheme
• In this, I/O device is treated as I/O device only
• Each I/O device uses 8 bits of address lines, control signals IOR’ and
IOW’.
• 8 bit address is transferred on both address groups: A0 to A7 and A8 to
A15.
For Example: address of I/O device is 50H
continued
• Two instructions available for data transfer between an I/O device and
microprocessor.
IN address
OUT address
Memory Mapped I/O scheme
• I/O devices treated as memory locations
• There will be no separation like memory or I/O.
• Each I/O device will have 16 bit address.
• The control signals used will be same as memory i.e MEMR’ and
MEMW’
• Instructions are:
• LDA,STA,STAX, LDAX, MOV A, M and MOV M,A
Comparison of Memory mapped & I/O
mapped I/O scheme
Memory Mapped I/O mapped
16 bit device address is used 8 bit device address is used
Data transfer between any general purpose register Data is transfer only between accumulator and I/O
and I/O port port
More hardware is required to decode 16 bit address Less hardware is required
Arithmetic or logic operation can be directly Arithmetic or logic operation cannot be directly
performed performed
All instructions like LDA, LDAX STA STAX, MOV A,M etc IN and OUT instructions are used
are used
A large number of I/O ports can be interfaced Only 256 ports can be interfaced
Less memory space is available due to partitioning Whole address is available.
Devices are accessed by memory read and memory Devices are accessed by I/O read and I/O write cycle
write cycle
Features of 8257 DMA Controller:
The Features of Microprocessor 8257 DMA Controller are follows,
1. It is a programmable; 4-channel, direct memory access controller. Each channel can
be programmed individually. Therefore, we can interface 4 input/output devices with
8257.
2. Each channel includes a 16-bit DMA address register and a 14-bit counter. DMA
address register gives the address of the memory location and counter specifies the
number of DMA cycles to be performed. As counter is 14-bit, each channel can transfer
214 (16 kbytes) without intervention of microprocessor.
3. It maintains the DMA cycle count for each channel and activates a control signal TC
(Terminal count) to indicate the peripheral that the programmed number of DMA
cycles are complete.
4. It provides another control signal MARK to indicate peripheral that the current DMA
cycle is the 128th cycle since the previous MARK output.
5. It has priority logic that resolves the peripherals requests. The priority logic can be
programmed to work in two modes, either in fixed mode or rotating priority mode.
6. It provides inhibit logic which can be used to inhibit individual channels.
7. It allows data transfer in two modes : burst mode and cycle steal (single byte
transfer) mode.
8. It can execute three DMA cycles : DMA read, DMA write and DMA verify.
9. Auto load Features of 8257 permits repeat block or block chaining operations.
10. It operates in two modes : slave and master.
11. When DMA is in master mode, AEN signal provided by 8257 allows to isolate CPU
buffers, latches and other devices from the system bus.
12. Extended write mode of 8257 prevents the unnecessary occurrence of wait states in
the Features of 8257; increasing the system throughput.
13. It operates on single TEL clock and it is completely TEL compatible.
14. It can be interfaced with all Intel
15. It transfers one byte of data in four clock cycles. Thus giving high transfer rate such
as 500 Kbytes/second at 2 MHz clock input.
16. Like 8085, Features of 8257 also has READY input which allows 8257 to interface
slower memory or I/O devices that can not meet bus setup times required by the 8257.