EE227 Computer Organization

and Architecture

Chapter # 3
Arithmetic For Computers
Today’s Topic
 Introduction

 Numerical Representation

 Algorithm for Binary Addition, Subtraction,

Multiplication & Division

2
Introduction
• Computer words are composed of bits; thus, words can
be represented as binary numbers.

• Integers can be represented either in decimal or binary

form, but what about the other numbers that commonly
occur? For example:

 What about fractions and other real numbers?

 What happens if an operation creates a number bigger than
can be represented?
 How does hardware really multiply or divide numbers?

• This chapter deals with representation of real numbers,

arithmetic algorithms, hardware that follows these
algorithms, and the implications of all this for instruction
3
sets.
 Binary Representation

• The binary number

01011000 00010101 00101110 11100111

Most significant bit Least significant bit

represents the quantity

0 x 231 + 1 x 230 + 0 x 229 + … + 1 x 20

• A 32-bit word can represent 232 numbers between

0 and 232-1
This is known as the unsigned representation as
we’re assuming that numbers are always positive

•Largest Number ? 4
ASCII Vs. Binary

• Character can be represented with an ASCII code

(8-bit)

•Does it make more sense to represent a decimal number

in ASCII?

• Hardware to implement arithmetic would be difficult

• What are the storage needs? How many bits does it

take to represent the decimal number 1,000,000,000 in
ASCII and in binary?
In binary: 30 bits (230 > 1 billion)
In ASCII: 10 characters, 8 bits per char = 80 bits
5
Possible Representations
Sign Magnitude: One's Complement Two's Complement

and positives; unique zero

000 = 0 000 = 0 000 = 0

unequal no. of negatives

ambiguous zero

ambiguous zero
001 = +1 001 = +1 001 = +1
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 =
+3
100 = 0 100 = -3 100 = -
4
101 = -1 101 = -2 101 = -
3
110 = -2 110 = -1 110 = -
2
111 = -3 111 = 0 111 = -1

6
Negative Numbers

32 bits can only represent 232 numbers – if we wish to also represent

negative numbers, we can represent 231 positive numbers (incl zero)
and 231 negative numbers

0000 0000 0000 0000 0000 0000 0000 0000 two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001 two = 1ten
…
0111 1111 1111 1111 1111 1111 1111 1111 two = 231-1

1000 0000 0000 0000 0000 0000 0000 0000 two = -231
1000 0000 0000 0000 0000 0000 0000 0001 two = -(231 – 1)
1000 0000 0000 0000 0000 0000 0000 0010 two = -(231 – 2)
…
1111 1111 1111 1111 1111 1111 1111 1110 two = -2
1111 1111 1111 1111 1111 1111 1111 1111 two = -1 7
 MIPS – 2’s complement

• 32 bit signed numbers:

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten
0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten maxint
...
0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten
0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten
1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten
...
minint
1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten
1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten
Negative integers are exactly those that have leftmost bit 1 8
2’s Complement
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001two = 1ten
…
0111 1111 1111 1111 1111 1111 1111 1111two = 231-1

1000 0000 0000 0000 0000 0000 0000 0000two = -231

1000 0000 0000 0000 0000 0000 0000 0001two = -(231 – 1)
1000 0000 0000 0000 0000 0000 0000 0010two = -(231 – 2)
…
1111 1111 1111 1111 1111 1111 1111 1110two = -2
1111 1111 1111 1111 1111 1111 1111 1111two = -1
Why is this representation favorable?
Consider the sum of 1 and -2 …. we get -1
Consider the sum of 2 and -1 …. we get +1

This format can directly undergo addition without any conversions!

Each number represents the quantity
x31 -231 + x30 230 + x29 229 + … + x1 21 + x0 20 9
2’s Complement
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001two = 1ten
…
0111 1111 1111 1111 1111 1111 1111 1111two = 231-1

1000 0000 0000 0000 0000 0000 0000 0000two = -231

1000 0000 0000 0000 0000 0000 0000 0001two = -(231 – 1)
1000 0000 0000 0000 0000 0000 0000 0010two = -(231 – 2)
…
1111 1111 1111 1111 1111 1111 1111 1110two = -2
1111 1111 1111 1111 1111 1111 1111 1111two = -1
Note that the sum of a number x and its inverted representation x’ always
equals a string of 1s (-1).
x + x’ = -1
x’ + 1 = -x … hence, can compute the negative of a number by
-x = x’ + 1 inverting all bits and adding 1

Similarly, the sum of x and –x gives us all zeroes, with a carry of 1

In reality, x + (-x) = 2n … hence the name 2’s complement 10
Example

• Compute the 32-bit 2’s complement representations

for the following decimal numbers:
5, -5, -6

11
Example

• Compute the 32-bit 2’s complement representations

for the following decimal numbers:
5, -5, -6

5: 0000 0000 0000 0000 0000 0000 0000 0101

-5: 1111 1111 1111 1111 1111 1111 1111 1011
-6: 1111 1111 1111 1111 1111 1111 1111 1010

Given -5, verify that negating and adding 1 yields the

number 5

12
Signed / Unsigned

• The hardware recognizes two formats:

unsigned (corresponding to the C declaration unsigned int)

-- all numbers are positive, a 1 in the most significant bit
just means it is a really large number

signed (C declaration is signed int or just int)

-- numbers can be +/- , a 1 in the MSB means the number
is negative

This distinction enables us to represent twice as many

numbers when we’re sure that we don’t need negatives
13
MIPS Instructions

Consider a comparison instruction:

slt $t0, $t1, $zero
and $t1 contains the 32-bit number 1111 01…01

What gets stored in $t0?

14
MIPS Instructions

Consider a comparison instruction:

slt $t0, $t1, $zero
and $t1 contains the 32-bit number 1111 01…01

What gets stored in $t0?

The result depends on whether $t1 is a signed or unsigned
number – the compiler/programmer must track this and
accordingly use either slt or sltu

slt $t0, $t1, $zero stores 1 in $t0

sltu $t0, $t1, $zero stores 0 in $t0

15
Sign Extension

• Occasionally, 16-bit signed numbers must be converted

into 32-bit signed numbers – for example, when doing an
add with an immediate operand

• The conversion is simple: take the most significant bit and

use it to fill up the additional bits on the left – known as
sign extension

So 210 goes from 0000 0000 0000 0010 to

0000 0000 0000 0000 0000 0000 0000 0010

and -210 goes from 1111 1111 1111 1110 to

1111 1111 1111 1111 1111 1111 1111 1110 16
Alternative Representations

• The following two (intuitive) representations were discarded

because they required additional conversion steps before
arithmetic could be performed on the numbers

 sign-and-magnitude: the most significant bit represents

+/- and the remaining bits express the magnitude

 one’s complement: -x is represented by inverting all

the bits of x

Both representations above suffer from two zeroes

17
Addition and Subtraction

• Addition is similar to decimal arithmetic

• For subtraction, simply add the negative number – hence,

subtract A-B involves negating B’s bits, adding 1 and A

Source: H&P textbook

18
Two’s Complement Addition
 Perform addition
Examples (4-bits):
0101 0110 1011 1001 1111
0001 0101 0111 1010 1110
Do these sums now!! Remember all registers are 4-bit including result register!
So you have to throw away the carry-out from the msb!!
 Have to beware of overflow : if the fixed number of bits (4, 8, 16,
32, etc.) in a register cannot represent the result of the operation
 Overflow does not mean there was a carry-out from the msb that
we lost (though it sounds like that!) – it means simply that the
result in the fixed-sized register is incorrect
 As can be seen from the above examples there are cases when
the result is correct even after losing the carry-out from the
msb 19
Detecting Overflow
 No overflow when adding a positive and a negative number
 No overflow when subtracting numbers with the same sign
 Overflow occurs when the result has “wrong” sign (verify!):

Operation Operand A Operand B Result

Indicating Overflow

A + B  0  0  0
A + B  0  0  0
A – B  0  0  0
A – B  0  0  0

20
Overflows

• For an unsigned number, overflow happens when the last carry (1)
cannot be accommodated

• For a signed number, overflow happens when the most significant bit
is not the same as every bit to its left
 when the sum of two positive numbers is a negative result
 when the sum of two negative numbers is a positive result

• MIPS allows addu and subu instructions that work with unsigned
integers and never flag an overflow – to detect the overflow, other
instructions will have to be executed

21
Effects of Overflow
 If an exception (interrupt) occurs
 control jumps to predefined address for exception
 interrupted address is saved for possible resumption

 We have just seen how to detect overflow for two’s complement

numbers in a computer. What about overflow with unsigned integers?
Unsigned integers are commonly used for memory addresses where
overflows are ignored.

 Don't always want to cause exception on overflow

 add, addi, sub cause exceptions on overflow
 addu, addiu, subu do not cause exceptions on overflow

22
Some Terms

23
 Multiplication Example
Multiplicand 1000ten
Multiplier x 1001ten
---------------
1000 Binary makes it easy
0000 multiplier bit 1 => copy multiplicand
(1 x multiplicand)
0000 multiplier bit 0 => place 0
1000 (0 x multiplicand)
----------------
Product 1001000ten
In every step
• multiplicand is shifted
• next bit of multiplier is examined (also a shifting step)
• if this bit is 1, shifted multiplicand is added to the product

24
 HW Algorithm 1
Start

Multiplier0 = 1 1. Test Multiplier0 = 0

Multiplier0
32-bit multiplicand starts at right half of multiplicand register

Multiplicand 1a. Add multiplicand to product and

Shift left place the result in Product register
64 bits

Multiplier
64-bit ALU Shift right
2. Shift the Multiplicand register left 1 bit
32 bits

Product
Control test
Write 3. Shift the Multiplier register right 1 bit
64 bits

Product register is initialized at 0

No: < 32 repetitions
Multiplicand register, product register, ALU are 32nd repetition?

64-bit wide; multiplier register is 32-bit wide

Yes: 32 repetitions

Done 25
 Shift-add Multiplier Version1
Start

Multiplier0 = 1 1. Test Multiplier0 = 0 Example: 0010 * 0011:

Multiplier0

Itera Step Multiplier Multiplicand Product

-tion
1a. Add multiplicand to product and
place the result in Product register 0 init 0011 0000 0010 0000 0000
values
1 1a 0011 0000 0010 0000 0010
2. Shift the Multiplicand register left 1 bit
2 0011 0000 0100 0000 0010
3 0001 0000 0100 0000 0010
2 …
3. Shift the Multiplier register right 1 bit

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done

26
Algorithm
Observation- Shift-add Multiplier Version1

 1 step per clock cycle  nearly 100 clock cycles to multiply two
32-bit numbers
 Half the bits in the multiplicand register always 0
 64-bit adder is wasted
 0’s inserted to right as multiplicand is shifted left
 least significant bits of product never
change once formed

 Intuition: instead of shifting multiplicand to left, shift product to

right…

27
HW Algorithm 2
Start

Multiplicand register, multiplier register, ALU

Multiplier0 = 1 Multiplier0 = 0
are 32-bit wide; product register is 64-bit wide; 1. Test
Multiplier0
multiplicand adds to left half of product register

Multiplicand 1a. Add multiplicand to the left half of

the product and place the result in
32 bits the left half of the Product register

Multiplier
32-bit ALU Shift right
32 bits 2. Shift the Product register right 1 bit

Shift right
Product Control test
Write
3. Shift the Multiplier register right 1 bit
64 bits

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done Algorithm
28
 Shift-add Multiplier Version2
Start

Multiplier0 = 1 Multiplier0 = 0
1. Test
Multiplier0 Example: 0010 * 0011:

Itera Step Multiplier Multiplicand Product

1a. Add multiplicand to the left half of
the product and place the result in
- tion
the left half of the Product register 0 init 0011 0010 0000 0000
values
1 1a 0011 0010 0010 0000
2. Shift the Product register right 1 bit 2 0011 0010 0001 0000

3 0001 0010 0001 0000

3. Shift the Multiplier register right 1 bit
2 …

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done

29
Algorithm
Observation- Shift-add Multiplier Version 2

 Each step the product register wastes space that exactly matches
the current size of the multiplier

 Intuition: combine multiplier register and product register…

30
 HW Algorithm 3
• 32-bit ALU and multiplicand is untouched Start

• the sum keeps shifting right

• at every step, number of bits in product + multiplier = 64,
hence, they share a single 64-bit register Product0 = 1 1. Test Product0 = 0
Product0
Multiplicand

32 bits
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
32-bit ALU

Shift right Control

Product
Write test 2. Shift the Product register right 1 bit
64 bits

No: < 32 repetitions

32nd repetition?

No separate multiplier register; multiplier

Yes: 32 repetitions
placed on right side of 64-bit product register
Algorithm
31
Done
 Shift-add Multiplier Version 3
Start

Example: 0010 * 0011:

Product0 = 1 1. Test Product0 = 0
Product0
Itera Step Multiplicand Product
-tion
0 init 0010 0000 0011
1a. Add multiplicand to the left half of values
the product and place the result in
the left half of the Product register 1 1a 0010 0010 0011
2 0010 0001 0001
2 …
2. Shift the Product register right 1 bit

No: < 32 repetitions

32nd repetition?
2 steps per bit because
Yes: 32 repetitions
multiplier & product combined
Done 32
Algorithm
Multiple Algorithm (1) Example

33
Signed Number Multiplication

• The previous algorithm also works for signed numbers

(negative numbers in 2’s complement form)

•Solution is to make both positive and remember whether

to negate product when done, i.e., leave out the sign bit,
run for 31 steps, then negate if multiplier and multiplicand
have opposite signs

• The product of two 32-bit numbers can be a 64-bit

number
-- hence, in MIPS, the product is saved in two 32-bit
registers
34
MIPS Instructions

mult $s2, $s3 computes the product and stores

it in two “internal” registers that
can be referred to as hi and lo

mfhi $s0 moves the value from hi into $s0

mflo $s1 moves the value from lo into $s1

Similarly for multu

35
Hardware Comparison

• Design basic hardware(1) easy to understand

• Optimize it (hardware 3) to take fewer transistor (smaller

ALU, smaller sets of registers ) fewer transistor is involved
as fewer bits are changing in every single cycle

• If our focus is performance enhancement not energy

efficiency then there can be another alternative hardware
design which can be implemented

•32 Chaned additions (the more transistors, the faster the

multiplicationis )
36
Fast Algorithm

• The previous algorithm

requires a clock to ensure that
the earlier addition has
completed before shifting

• This algorithm can quickly set

up most inputs – it then has to
wait for the result of each add
to propagate down – faster
because no clock is involved

-- Note: high transistor cost

37
Source: H&P textbook
Division(1)

1001ten Quotient
Divisor 1000ten | 1001010ten Dividend
-1000
10
101
1010
-1000
10ten Remainder

At every step,
• shift divisor right and compare it with current dividend
• if divisor is larger, shift 0 as the next bit of the quotient
• if divisor is smaller, subtract to get new dividend and shift 1
as the next bit of the quotient 38
Division(2)

39
 Division(3)

1001ten Quotient
Divisor 1000ten | 1001010ten Dividend

0001001010 0001001010 0000001010 0000001010

100000000000  0001000000 00001000000000001000
Quo: 0 000001 0000010 000001001

At every step,
• shift divisor right and compare it with current dividend
• if divisor is larger, shift 0 as the next bit of the quotient
• if divisor is smaller, subtract to get new dividend and shift 1
as the next bit of the quotient 40
Divide Example
• Divide 7ten (0000 0111two) by 2ten (0010two)

Iter Step Quot Divisor Remainder

0 Initial values
1

41
Divide Example
• Divide 7ten (0000 0111two) by 2ten (0010two)
Iter Step Quot Divisor Remainder
0 Initial values 0000 0010 0000 0000 0111
1 Rem = Rem – Div 0000 0010 0000 1110 0111
Rem < 0  +Div, shift 0 into Q 0000 0010 0000 0000 0111
Shift Div right 0000 0001 0000 0000 0111
2 Same steps as 1 0000 0001 0000 1111 0111
0000 0001 0000 0000 0111
0000 0000 1000 0000 0111
3 Same steps as 1 0000 0000 0100 0000 0111
4 Rem = Rem – Div 0000 0000 0100 0000 0011
Rem >= 0  shift 1 into Q 0001 0000 0100 0000 0011
Shift Div right 0001 0000 0010 0000 0011
5 Same steps as 4 0011 0000 0001 0000 0001
42
Divide Example
• Divide 7ten (0000 0111two) by 2ten (0010two)

43
Hardware for Division

Source: H&P textbook

A comparison requires a subtract; the sign of the result is

examined; if the result is negative, the divisor must be added back

Similar to multiply, results are placed in Hi (remainder) and Lo (quotient)

44
 Hardware for Division-Basic Algorithm
Start

1. Subtract the Divisor register from the

Remainder register and place the
32-bit divisor starts at left half of divisor register result in the Remainder register

Divisor Quotient register is

Shift right Remainder –> 0 Remainder < 0
initialized to be 0 Test Remainder
64 bits

Quotient
64-bit ALU Shift left
2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
32 bits setting the new rightmost bit to 1 the Divisor register to the Remainder
register and place the sum in the
Remainder Control Remainder register. Also shift the
Write test Quotient register to the left, setting the
new least significant bit to 0
64 bits

Remainder register is initialized with the dividend at right

3. Shift the Divisor register right 1 bit

Divisor register, remainder register, ALU are

64-bit wide; quotient register is 32-bit wide No: < 33 repetitions
33rd repetition?

Yes: 33 repetitions
Algorithm 45
Done
 Hardware for Division-Basic Algorithm
Start

Example: 0111 / 0010:

1. Subtract the Divisor register from the
Remainder register and place the
result in the Remainder register
Itera- Step Quotient Divisor Remainder
tion
0 init 0000 0010 0000 0000 0111
Remainder –> 0 Remainder < 0 1 1 0000 0010 0000 1110 0111
Test Remainder
2b 0000 0010 0000 0000 0111
3 0000 0001 0000 0000 0111
2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
2 …
setting the new rightmost bit to 1 the Divisor register to the Remainder
register and place the sum in the
3
Remainder register. Also shift the 4
Quotient register to the left, setting the
new least significant bit to 0 5

3. Shift the Divisor register right 1 bit

No: < 33 repetitions

33rd repetition?

Yes: 33 repetitions

Done
46
Efficient Division

47
Divisions Involving Negatives

• Simplest solution: convert to positive and adjust sign later

• Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Remainder

+7 div +2 Quo = Rem =

-7 div +2 Quo = Rem =
+7 div -2 Quo = Rem =
-7 div -2 Quo = Rem =

48
Divisions involving Negatives

• Simplest solution: convert to positive and adjust sign later

• Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Remainder

+7 div +2 Quo = +3 Rem = +1

-7 div +2 Quo = -3 Rem = -1
+7 div -2 Quo = -3 Rem = +1
-7 div -2 Quo = +3 Rem = -1

Convention: Dividend and remainder have the same sign

Quotient is negative if signs disagree
These rules fulfil the equation above

49
Floating Point(1)

50
Floating Point(2)

 We need a way to represent

 numbers with fractions, e.g., 3.1416
 very small numbers (in absolute value), e.g., .00000000023
 very large numbers (in absolute value) , e.g., –3.15576 * 1046
 Representation:
 scientific: sign, exponent, significand form:
 (–1)sign *significand *2exponent . E.g., –101.001101 * 2111001
 more bits for significand gives more accuracy
 more bits for exponent increases range
 if 1  significand  10two(=2ten) then number is normalized, except
for number 0 which is normalized to significand 0
 E.g., –101.001101 * 2111001 = –1.01001101 * 2111011 (normalized)
51
Floating Point(3)

• Normalized scientific notation: single non-zero digit to the

left of the decimal (binary) point – example: 3.5 x 109

• 1.010001 x 2-5two = (1 + 0 x 2-1 + 1 x 2-2 + … + 1 x 2-6) x 2-5ten

• A standard notation enables easy exchange of data between

machines and simplifies hardware algorithms – the
IEEE 754 standard defines how floating point numbers
are represented

52
Sign and Magnitude Representation

Sign Exponent Fraction

1 bit 8 bits 23 bits
S E F

• More exponent bits  wider range of numbers (not necessarily more

numbers – recall there are infinite real numbers)

• More fraction bits  higher precision

• Register value = (-1)S x F x 2E

• Since we are only representing normalized numbers, we are

guaranteed that the number is of the form 1.xxxx..
Hence, in IEEE 754 standard, the 1 is implicit
Register value = (-1)S x (1 + F) x 2E
53
Sign and Magnitude Representation

Sign Exponent Fraction

1 bit 8 bits 23 bits
S E F

• Largest number that can be represented:

• Smallest number that can be represented:

54
Sign and Magnitude Representation
Sign Exponent Fraction
1 bit 8 bits 23 bits
S E F

• Largest number that can be represented: 2.0 x 2 128 = 2.0 x 1038

• Smallest number that can be represented: 1.0 x 2-127 = 2.0 x 10-38

• Overflow: when representing a number larger than the one above;

Underflow: when representing a number smaller than the one above

• Double precision format: occupies two 32-bit registers:

Largest: Smallest:
Sign Exponent Fraction
1 bit 11 bits 52 bits
S E F 55
Exponent Representation

• To simplify sort, sign was placed as the first bit

• For a similar reason, the representation of the exponent is also

modified: in order to use integer compares, it would be preferable to
have the smallest exponent as 00…0 and the largest exponent as 11…1

• This is the biased notation, where a bias is subtracted from the

exponent field to yield the true exponent

• IEEE 754 single-precision uses a bias of 127 (since the exponent

must have values between -127 and 128)…double precision uses
a bias of 1023

Final representation: (-1)S x (1 + Fraction) x 2(Exponent – Bias)

56
Bias and Fraction field
Example(continue)
Example (continue)
Examples

Final representation: (-1)S x (1 + Fraction) x 2(Exponent – Bias)

• Represent -0.75ten in single and double-precision formats

Single: (1 + 8 + 23)

Double: (1 + 11 + 52)

61
Examples

Final representation: (-1)S x (1 + Fraction) x 2(Exponent – Bias)

• Represent -0.75ten in single and double-precision formats

Single: (1 + 8 + 23)
1 0111 1110 1000…000

Double: (1 + 11 + 52)
1 0111 1111 110 1000…000

• What decimal number is represented by the following

single-precision number?
1 1000 0001 01000…0000 62
Opposite Way

Sign Exponent Fraction

- 129 0x2-1+1x2-2 =0.25

FP Addition

• Consider the following decimal example (can maintain

only 4 decimal digits and 2 exponent digits)

9.999 x 101 + 1.610 x 10-1

Convert to the larger exponent:
9.999 x 101 + 0.016 x 101
Add
10.015 x 101
Normalize
1.0015 x 102
Check for overflow/underflow
Round
1.002 x 102
Re-normalize 65
FP Addition

• Consider the following decimal example (can maintain

only 4 decimal digits and 2 exponent digits)

9.999 x 101 + 1.610 x 10-1

Convert to the larger exponent:
9.999 x 101 + 0.016 x 101
Add
10.015 x 101
Normalize If we had more fraction bits,
these errors would be minimized
1.0015 x 102
Check for overflow/underflow
Round
1.002 x 102
Re-normalize 66