Introduction to Advanced

Microcontrollers
AVR Family , MSP430
Contents
• History of AVR Microcontrollers
• AVR family Overview
• Simplified Block Diagram
• Architecture
• General Purpose Registers
• Data Memory & I/O Memory
• AVR Status Register
• Program Counter & Program ROM Space
• Stack & Stack Pointer
•Addressing Modes
•Instruction Set
•ATmega32 Pin Diagram
•Delay in AVR & Pipelining
History & Features of AVR Microcontroller
• Basic architecture developed by students(Alf-Egil Bogen & Vegard Wollan) of
Norwegian Institute of Technology and then was bought and developed by
Atmel in 1996.
• AVR derived either as Advanced virtual RISC or Alf & Vegard RISC.
• Except AVR32 all AVR microcontrollers are 8 bit. i.e. they can process 8 bit at
a time.
Features:
• AVR is 8 bit RISC single chip microcontroller with Harvard architecture.
• On chip Programme ROM
• On chip Data RAM
• Data EEPROM
• Timers
• I/O Ports
• Additional Features like ADC, PWM & serial interfaces like USART, SPI, I2C, USB, CAN…
AVR Family Overview
• Classified in 4 broad groups:
• Classic
• Mega
• Tiny
• Special Purpose
• Classic(AT90Sxxxx): Original AVR now replaced by newer versions
• Mega(Atmega):
• Powerful and Popularly used. Atmega32 is most widely used device in this family.
• Programme Memory (4K to 256 K)
• Package:28 pins to 100 pins(DIP)
• Extensive Peripheral Set
• Extended instruction set (120 instructions)
Simplified Block Diagram
• AVR microcontrollers have RAM , Programme ROM and EEPROM.
• AVR have 8 Mbytes Programme ROM space but actual ROM size for
various family members varies from 1KB to 256 KB.
• AVR uses flash memory which can be developed fast (in few seconds
compared to 20 minutes for UV-EPROM)
• AVR has maximum of 64K Data RAM space. RAM space has three
components: general purpose registers , I/O memory and internal
SRAM.
• There are 32 general purpose registers in all AVRs bur I/O memory
and internal SRAM varies from chip to chip.
• It has small Data EEPROM varying from 0.5 KB to 4KB.
• Like other microcontrollers it has timers, interrupt, ports and other
supporting peripherals.
• I/O pins depends on total pins in package.AVR can have 3 to 86 pins
for I/O for 8 to 100 pin packaging devices respectively.
• Most AVRs have ADC, Timers and USART as standard peripherals.
• In AVR there is a 10 bit ADC and number of ADC channels varies upto
16 depending on package pins.
• AVR can have upto 6 timers apart from watchdog timer.
• Most of AVRs come with USART and have I2C and SPI(Serial
Periphearal Interface) bus but some may have USB or CAN as well.
Watchdog Timer in AVR
• What Is a Watchdog Timer?
• A watchdog timer is a specialized timer module that helps a
microprocessor to recover from malfunctions.
• If a watchdog timer reaches the end of its counting period, it resets the
entire processor system.
• Thus, a watchdog timer can be configured such that it will reach the
end of its counting period only if a processor failure has occurred, and
by forcing a system reset, the watchdog timer helps the processor to
escape from the failure mode and continue normal operation.
• WDT has two types :
• Windowed & Non-Windowed
• In Non-windowed WDT, there is
upper limit for count. If WDT is
provide service(attention) before
the upper limit is reached,
processor is not reset and
everything OK.
• For Windowed WDT, there is
lower limit of count apart from
upper limit.
• If WDT is attended after reaching
lower limit and before upper limit,
everything is OK.
• But if service is provided even
before reaching lower limit,
processor is reset.
 General Purpose Resistors in AVR
• GPRs in CPU are used to store information temporarily.
• In AVR there are 32 general purpose registers. Most of the registers in AVR
are of 8 bits.
• Those are R0 to R31, are located in lowest location of Memory (RAM).
• They can be used to store data by
Any arithmetic or logical instruction.
AVR memory
• In AVR there is Code Memory Space & Data Memory Space
• Program is stored in Code Memory Space and Data in Data Memory
Space.
• Data Memory consist of three parts:
• GPRs; I/O memory and Internal Data SRAM.
• There are 32 GPRs and always occupies addresses from 00H to 1F H
• AVR has two memory space:
• Code Memory & Data Memory Space
• Code Memory Space: Code memory stores the program/instructions in
AVR.
• AVR flash memory is 16 bit wide. i.e. each memory location can store 16
bits data.
• Program counter is used by CPU to point to the address of next instruction
to be executed.
• Program Counter in AVR family can be upto 22 bits wide and can access
upto 4M locations.i.e. the address range for this can be from 000000 H to
3FFFFF H.
Data Memory
• It is internal Data SRAM. It is generally called ass scratch pad RAM.
• Each location can be directly accessed using its address.
• It is 8 bits i.e. 1 Byte wide and is used to store any 8 bit data in each
location.
I/O Memory(SFRs)
• I/O memory contains specific function registers like status registers,
timers, serial communication, I/O ports , ADC and so on.
• I/O memory has 8 bit wide registers.
• Most of AVR family members have at least 64 bytes of I/O meory. This
is called as standard I/O memory.
• For AVRs such as ATMega64, ATMega128 & ATMega256 have more
than 64 bytes of I/O memory and it is called as extended I/O memory.
AVR status register

• Status register is 8 bit register.Also called flag register.

• C,Z,N,V,S & H are conditional flags which are used to perform conditional jumps.
• C-Carry flag :sets when carry out of D7 bit.
• Z-Zero flag: Sets when result is all zero.
• N-Negative flag: If D7 bit of result is 0 then result is positive so N=0.If D7 bit is 1 then result is
negative and N=1.
• V-Overflow flag: This sets when result of signed operation is too large such that result overflows
in sign bit.
• S-Sign flag: This flag is EX-OR of N & V flags.
• H-Half carry flag: If there is carry from D3 to D4 bit of arithmetic operation then its Set.
• I-Interrupt flag: This is Interrupt Enable or Disable flag. I=1 interrupt Enabled, I=0 interrupt
disabled.
Addressing Modes of AVR
• Addressing Modes of AVR Microcontroller - Bing video
• Addressing Modes of AVR Microcontroller – YouTube
 Addressing Modes of AVR
• The way in which data is accessed from
register/memory/immediately is called addressing mode.
• AVR has 5 different addressing modes:
• Single register(Immediate)
• Register or 2 register
• Direct or I/O direct
• Register Indirect
• Flash indirect
• Single Register(Immediate): Operand is in single register or given
immediate data.
e.g. NEG R18; COM R19; LDI R19, 0X25; ANDI R19, 0b01000000
• Two Register: Two registers are used to hold data.
e.g. ADD R19,R23 ; SUB R23, R16 ; MOV R30, R29 ; AND R16, R17
• Dierct : Access data from memory using direct address of the memory
location.
e.g.LDS R19,0X560 ; Load storage(memory) i.e.load data from location
0X560 to R19 register
STS 0X520, R18 ; Store in storage i.e. Save data from R18 into 0X520 RAM
memory location.
• I/O direct: To access I/O register by direct address.
e.g. IN R18, 0X16 ; Content of location 16 h(PINB)
OUT Ox15, R18 ; content of location 15h (PORT C)

Direct Addressing vs I/O addressing

OUT R19, 0X15; I/O addressing (PORT C)
STS R19, 0X35 ; Direct addressing(PORT C)

IN R18, 0X12 ; I/O addressing (PORT D)

LDS R18, 0X32; Direct addressing (PORT D)

# for accessing these RAM locations as I/O; only

IN and OUT instructions are used.
• Register Indirect: This mode is used to indirectly access data memory location.
Register X,Y,Z are used as memory pointer. X,Y,Z registers are the 16 bit registers
which can be divided into two 8 bit registers.These X,Y,Z are nothing but the R26
to R31 general purpose registers Which are combined to form 16 bit X,Y,Z
registers respectively as shown in diagram.
e.g.
LDI XL, 0X30
LDI XH, 0X01
LD R18,X
With this instruction data in the location
0X130(which is available in X register) is R18
X 0X130
loaded in R18 register. 0X130 0X 26 0X 26
• Flash Indirect: Loading data from ROM using pointers.
• e.g. LPM Rd, Z ; Rd can be R0-R31.LPM stands for load from
permanent memory.
• LPM Rd, Z+ ; After copying the data from address given in Z register,
address in Z will be automatically incremented.
ATMega32 pin configuration
Pin No. Pin name Description Alternate Function

1 PB0(XCK/T0) Pin 0 of PORTB T0( Timer0 External Counter Input)

XCK ( USART External Clock I/O)

2 PB1(T1) Pin 1 of PORTB T1(Timer1 External Counter Input)

3 PB2(INT2/AIN0) Pin 2 of PORTB AIN0(Analog Comparator Positive

I/P)
INT2( External Interrupt 2 Input)
4 PB3(OC0/AIN1) Pin 3 of PORTB AIN1(Analog Comparator Negative
I/P)
OC0 (Timer0 Output Compare
Match Output)
5 PB4(SS) Pin 4 of PORTB SS (SPI Slave Select Input). This pin is low when
controller acts as slave.
[Serial Peripheral Interface (SPI) for
programming]
6 PB5(MOSI) Pin 5 of PORTB MOSI (Master Output Slave Input). When
controller acts as slave, the data is received by
this pin.
[Serial Peripheral Interface (SPI) for
programming]
7 PB6(MISO) Pin 6 of PORTB MISO (Master Input Slave Output). When
controller acts as slave, the data is sent to master
by this controller through this pin.

[Serial Peripheral Interface (SPI) for

programming]
8 PB7(SCK) Pin 7 of PORTB SCK (SPI Bus Serial Clock). This is the clock
shared between this controller and other system for
accurate data transfer.
[Serial Peripheral Interface (SPI) for
9 RESET Reset Pin, Active Pulled HIGH to RESET controller.
Low Reset
10 Vcc Vcc = +5V
11 GND GROUND
12 XTAL2 Connected to
Crystal Oscillator
13 XTAL1 Connected to
Crystal Oscillator
14 PD0(RXD)Pin 0 of PORTD RXD (USART Input Pin)

USART Serial Communication

Interface
[Can be used for programming]
15 PD1(TXD) Pin 1 of PORTD TXD (USART Output Pin)
USART Serial Communication Interface
[Can be used for programming]
16 PD2(INT0) Pin 2 of PORTD External Interrupt INT0
17 PD3(INT1) Pin 3 of PORTD External Interrupt INT1
18 PD4(OC1B) Pin 4 of PORTD PWM Channel Outputs
19 PD5(OC1A) Pin 5 of PORTD
20 PD6(ICP) Pin 6 of PORTD Timer/Counter1 Input Capture Pin
21 PD7 (OC2) Pin 7 of PORTD Timer/Counter2 Output Compare Match Output
22 PC0 (SCL) Pin 0 of PORTC TWI Interface
23 PC1 (SDA) Pin 1 of PORTC
24 PC2 (TCK) Pin 2 of PORTC JTAG Interface
25 PC3 (TMS) Pin 3 of PORTC
26 PC4 (TDO) Pin 4 of PORTC
27 PC5(TDI) Pin 5 of PORTC
28 PC6 (TOSC1) Pin 6of PORTC
29 PC7 Pin 7 of PORTC Timer Oscillator Pin 2
(TOSC2)
30 AVcc Vcc for Internal ADC Converter

31 GND GROUND

32 AREF Analog Reference Pin for ADC

33 PA7 (ADC7) Pin 7 of PORTA ADC (Analog to Digital Converter) Channel 7

34 PA6 (ADC6) Pin 6 of PORTA ADC (Analog to Digital Converter) Channel 6

35 PA5 (ADC5) Pin 5 of PORTA ADC (Analog to Digital Converter) Channel 5

36 PA4 (ADC4) Pin 4 of PORTA ADC (Analog to Digital Converter) Channel 4

37 PA3 (ADC3) Pin 3 of PORTA ADC (Analog to Digital Converter) Channel 3

38 PA2 (ADC2) Pin 2 of PORTA ADC (Analog to Digital Converter) Channel 2

39 PA1 (ADC1) Pin 1 of PORTA ADC (Analog to Digital Converter) Channel 1

40 PA0 (ADC0) Pin 0 of PORTA ADC (Analog to Digital Converter) Channel 0

MSP430 Microcontroller
• The MSP430F2013 is an ultra-low-power mixed signal
microcontroller with a built-in 16-bit timer and ten I/O pins. In
addition, MSP430F2013 has built-in communication capability
using synchronous protocols (SPI or I2C) and a 16-bit sigma-
delta A/D converter.
• The architecture, combined with five low-power modes is
optimized to achieve extended battery life in portable
measurement applications. The device features a powerful 16-
bit RISC CPU, 16-bit registers, and constant generators that
contribute to maximum code efficiency. The digitally controlled
oscillator (DCO) allows wake-up from low-power modes to
active mode in less than 1 µs.
• CPU is 16-Bit RISC Architecture with The Clock with Internal Frequencies up to 16 MHz,
• -The emulation, JTAG interface and Spy-Bi-Wire are used to communicate with a desktop computer when downloading a program and for
debugging.
• -Low Supply Voltage Range 1.8 V to 3.6 V
• -Ultra-Low Power Consumption
• 1. Active Mode: 220 µA at 1 MHz, 2.2 V
• 2. Standby Mode: 0.5 µA
• 3. Off Mode: 0.1 µA
• -Five Power-Saving Modes
• -Ultra-Fast Wake-Up from Standby Mode in Less Than 1 µs
• -The main blocks are linked by the memory address bus (MAB) and memory data bus (MDB).
• -The MSP430 has flash memory of 2KB, and 128 bytes of RAM.
• -Six blocks are shown for peripheral functions include
• 1. Port P1: 8 input/output pins with interrupt capability,
• 2. Port P2: 2 input/output pins with interrupt capability,
• 3. 16-Bit Timer_A with Two Capture/Compare Registers,
• 4. A watchdog timer.
• 5. The universal serial interface (USI)
• 6. 16-Bit sigma–delta analog-to-digital converter (SD16_A)
• -The brownout protection comes into action if the supply voltage drops to a dangerous level.
• -There are ground and power supply connections. Ground is labeled VSS and is taken to define 0V. The supply connection is VCC.
MSP430 Family Features
• The MSP430 family currently consists of three subfamilies:
 MSP430C31x Hardware Item MSP430C31X MSP430C32X MSP430C33X
 MSP430C32x 14 bit ADC No Yes No
 MSP430C33x 16 bit Timer_A No No Yes
Basic Timer Yes Yes Yes
FLL Oscillator Yes Yes Yes
HW/SW UART Yes Yes Yes
HW Multiplier No No Yes
I/O port with interrupt 8 8 24
I/O port without interrupt 0 0 16
LCD Segment Lines 23 21 30
Package 56SSOP 64QFP 100QFP
Universal Timer/Port Module Yes Yes Yes
USART(SPI/ SCI) No No Yes
Watchdog Timer Yes Yes Yes
Advantages of MSP430 Architecture
• RISC architecture without RISC disadvantages:
 The RISC architecture provides a limited number of powerful instructions,numerous registers, and single-
cycle execution times.
 The more traditional microcomputer features provide addressing modesfor all instructions. This functionality
is further enhanced with 100% orthogonality,allowing any instruction to be used with any addressing mode.

• Real-Time Capability With Ultra-Low Power Consumption:

 No second high frequency crystal is used — inherent delays can range from 20 ms to 200 ms until oscillator
stability is reached
 Instead, a sophisticated FLL system clock generator is used — generator output frequency (MCLK) reaches
the nominal frequency within 8 cyclesafter activation from low power mode 3 (LPM3) or sleep mode.

• Digitally Controlled Oscillator Stability

• The digitally controlled oscillator (DCO) is voltage and temperature dependent,which does not mean that its
frequency is not stable.
• During the activemode, the integral error is corrected to approximately zero every 30.5 ms . Thisis
accomplished by switching between two different DCO frequencies. Onefrequency is higher than the
programmed MCLK frequency and the other islower, causing the errors to essentially cancel-out. The two
DCO frequenciesare interlaced as much as possible to provide the smallest possible error at any
given time.
Low power feature of MSP430
• The design of the MSP430 was driven by the need to provide full real-time
capability while still exhibiting extremely low power consumption.
• Average power consumption is reduced to the minimum by running the CPU and
certain other
functions of the MSP430 only when it is necessary.
• The rest of the time (the majority of the time), power is conserved by keeping
only selected low-power peripheral functions active.
• But to have a true real-time capability, the device must be able to shift from a
low-power mode with the CPU off to a fully active mode with the CPU and all
other device functions operating nominally in a very short time. This was
accomplished primarily with the design of the system clock:

The RISC architecture provides a limited number of powerful instructions,numerous

registers, and single-cycle execution times.
The more traditional microcomputer features provide addressing modesfor all
instructions. This functionality is further enhanced with 100% orthogonality,allowing
any instruction to be used with any addressing mode.