Chemical Mechanical Planarization

Class 15
04/05/2024
 Accelerated testing:
• Under normal operating condition, the time
required to observe failure in a device is very high.
• Accelerated testing: to study the failure chara by
accelerating the mechanisms that cause devices to
fail.
– Temperature
– Voltage
– Current
– Humidity
– Temperature cycling
 Temperature acceleration
• Major cause of failure: chemical, physical
processes.
• Accelerated by temperature.
• If R is the reaction rate at which these
processes proceed,
R  R0 exp(  Ea kT )
t1  Ea  1 1 
Accelerati onFactor   exp    
t2  kT  T1 T2 
• Assumes failure reaction is linear in time.
Voltage and current acceleration
• Accelerates failure caused by dielectric breakdown,
interface charge accumulation, charge injection, corrosion.
• Variations applicable for voltage is limited as most ICs
doesn’t work properly if applied voltage is beyond the
specified range.
• Studies indicate that R of failure mechanism is
proportional to a power of applied voltage.
 (T )
R (T ,V )  R0 (T )V
• Different stages in case of dielectric breakdown. Operation
at an increased voltage is more in the nature of burn-in.
• Current acceleration: for failure due to electromigration.
Same relationship for R as above.
 Stress dependent activation energy.

• Eyring model: to understand thermally and

stress activated failure mechanisms.
– Assumes that the energy required for the reaction
to take place is affected by applied stress(V or I).

 a (T ) S   Q 
R sinh   exp  
 kT   kT 
a (T )  kT (T )
Q  Ea 0  a (T ) S B
 Humidity-Temperature acceleration
• Possible failure mechanism: presence of water
vapor in the chip.
– Permeates plastic packaging material in two steps
• Transports contaminants from the surface of package
through plastic and leaches impurities from packaging
material itself.
• Diffusion of contaminated water vapor through
passivation layer of chip. Slow process. Determines
reaction rate of failure mechanism.
• Causes electrochemical corrosion.
 Burn-in
• Manufactured device shows existence of early failure.
• Photoresist or etching defects (open or shorts).
• Contamination on chip or in package
• Scratches.
• Weak chip or wire bonds
• Partially cracked chip or package
• Burn-in: operation of device for a period of time during
which most of the devices subjected to early failure
actually fails.
• Acceleration depends on mechanism contributing to
early failure.
 Failure mechanisms
• Electrostatic discharge damage:
• Voltages higher than breakdown voltage of gate oxide may be
placed on the device during handling.
• Major source: triboelectricity.
• Burn-in cannot reduce this. Actually can increase early failure
rate.
• Input and output terminals are designed with protection network
to provide path for discharge of current and protect gate oxide.
• Alpha particle induced soft errors:
• Emitted by U and Th occurring in packaging materials.
• Soft errors: random failure not related to physically defective
device.
• Eg: Loss of information stored.
 Failure Rate
• Failure Rate
– A system such as a calculator that made of many
semiconductor devices is put in operation for the
purpose of calculation, would have a certain failure rate ,
– which means it may fail after certain number of
operating hour. Thus, a calculator (system) has failure
rate with respect to operating time. The question is if
such failure is acceptable to end-user.
– Let’s take another example. A certain failure rate of the
system in a commercial aircraft is it acceptable to
airtravelling passengers?
• The failure rate () of a semiconductor device
implemented in the system is defined as
= No of Failure/No of transistor x period of operation

• If a system contains 100,000 transistors then the failure

rate () from one month operation is equal to
= No of Failure/No of transistor x period of operation
= 1 Failure/1x10-5x720hrs

which is equal to 14x10-9 Failure/Device-hour.

• If the unit of failure is defined to be 1 Failure Unit = 1 FIT = 1
Failure/10-9 Device-hour

• If one now considers a system that has 225 integrated circuits

and the failure rate of integrated circuit is 100 FIT. One can
calculate the mean time to a failure using above equation.
• Thus,
Period of operation< 1 Failure/ No of transistor x  =
1Failure/225 x100 x 10-9 = 4.44x104 hrs, which is
equal to 5.13 years.
• The percentage of failure per month shall be
100x10-9 x225x720x100% = 1.62%.
• Based on the above discussed example, one would see that it is time
consuming before a failure is shown out. We cannot be waiting for
5.13 years to see a failure is shown out to calculate the failure rate of a
system.
• One ought to have a developed method by sample testing to predict
the failure rate of the system. In this section, it discusses the methods
to quantitatively measure and predict device failure rate, and to
identify and eliminate the failure mechanism.

• If a device or system is operating at time t = 0. The probability that the

device will fail at or before time t is given by the function F(t). This is a
cumulative distribution function cdf with the following properties.
•

The reliability function R(t) is a probability that the device will

survive to time t without failure. Thus, the reliability function
R(t) is related to fail function by equation below
 R(t) = 1- F(t)
• The derivative of fail function F(t) with respect
to time is known as the probability density
function pdf and is represented by f(t). Thus,
the pdf is related to the cdf by
F(t) =d/dt F(t)
or the cumulative function
• Similarly the reliability function

And

The term failure rate is referred to as instantaneous fail rate and not average

The fraction of devices that are good at time t and that fails by time t+Δt is given by
F(t+t) –F(t) = R(t) – R(t+  t)
The average failure rate during the time interval  is given by
Average failure rate =1/  (R(t) – R(t+ t)/R(t)
In the limit as  approaches zero, this becomes the instantaneous failure rate () (t), which is
given by

Integrating equation it becomes

 Thus, the reliability function R(t) is given by

A common measure of reliability is the mean time to failure

(MTTF) of the device or system, which is defined as

MTTF is the device’s average age at failure for a population whose

reliability function is R(t) with probability density function f(t).
• During the early life of the device, the failure rate is high but it decreases as
time passed. The failure during this period is called infant mortality failure.

• The causes of the early failure are generally fabrication and assembly related
defects such as wire problem, micro-crack, over etch, photoresist residue,
contamination, electrostatic defect etc. The defects can be wiped out by
accelerated life test and followed by a final test to segregate them.

• The steady useful life period, the failure rate is normally low and the rate of
failure is also fairly constant. Device failure in this period is a result of a large
number of fabrication and assembly unrelated causes such as mishandling,
applying wrong stimulant etc.

• The wear out period is the old age period, whereby the device has reached the
end of its life.
 Problems
1. A disk drive's MTBF number may be 1,200,000 hours
and the disk drive may be running 24 hours a day, seven
days a week. One year has 8,760 hours. Calculate the
percentage failure? ( Ans-0.73%)
• A disk drive's MTBF number may be 700,000 hours and
the disk drive may be running 2400 hours a year.
Calculate the percentage failure ? ( Ans-0.34%)
2. Define the following terms: Failure Rate; Cumulative
distribution function; Density function; Mean time
between failure. 3
3. Define the relationship between cumulative
distribution function (cdf) F(t) and the density function
f(t).
Packaging
 Materials
• Ceramic
– Good heat conductivity
– Hermetic
– Expensive ( often more expensive than chip itself !)
• Metal (has been used internally in IBM)
– Good heat conductivity
– Hermetic
– Electrical conductive (must be mixed with other material)
• Plastic
– Cheap
– Poor heat conductivity
Can be improved by incorporating metallic heat plate.
 Cooling
• Package must transport heat from IC to
environment
• Heat removed from package by:
– Air: Natural air flow, Forced air flow
improved by mounting heat sink
– PCB: Transported to PCB by package pins
– Liquid: Used in large mainframe computers

Resistive equivalent

Heat sink
IC dice Package
I = heat power
V= temperature
R = K/watt

PCB
• Package types: 60 layers MCM substrate

– Below 1 watt: Plastic

– Below 5 watt: Standard ceramic
– Up to 30 watt: Special
Active heat sink Water cooled mainframe computer
Passive heat sink
 Requirements to package
• Protect circuit from external environment
• Protect circuit during production of PCB
• Mechanical interface to PCB
• Interface for production testing
• Good signal transfer between chip and PCB
• Good power supply to IC
• Cooling
• Small
• Cheap
 Chip mounting
• Pin through hole
– Pins traversing PCB
– Easy manual mounting
– Problem passing signals between pins on PCB (All layers)
– Limited density
• Surface Mount Devices (SMD)
– Small footprint on surface of PCB
– Special machines required for mounting
– No blocking of wires on lower PCB layers
– High density
•
Traditional
DIL (Dual In Line)
packages
Package inductance:
• Low pin count 1 - 20 nH

• Large
• PGA (Pin Grid Array)
• High pin count (up to 400)
• Previously used for most CPU’s
• PLCC (Plastic leaded chip carrier
• Limited pin count (max 84)
• Large
• Cheap
• SMD
• QFP (Quarter Flat pack)
• High pin count (up to 300)
• small
• Cheap
• SMD
 New package types
• BGA (Ball Grid Array)
• Small solder balls to
connect to board
• small Package inductance:
1 - 5 nH

• High pin count

• Cheap
• Low inductance
• CSP (Chip scale Packaging)
• Similar to BGA but smaller and thinner
• Very small packages
• MCP (Multi Chip Package)
– Mixing of several technologies in same component
– Yield improvement by making two chips instead of one

P6: processor + second level cache

 Chip to package connection
• Wire bonding
– Only periphery of chip available for IO connections
– Mechanical bonding of one pin at a time (sequential)
– Cooling from back of chip
– High inductance (~1nH)

• Flip-chip
– Whole chip area available for IO connections
– Automatic alignment
– One step process (parallel)
– Cooling via balls (front) and back if required
– Thermal matching between chip and substrate required
– Low inductance (~0.1nH)
https://www.youtube.com/watch?v=mvZ1dJuv
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