DIGITAL SYSTEM DESIGN

Text Book:
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital
Logic with Verilog Design (3e), Tata McGraw Hill 2014.

The slides in this document are prepared using the above text book
 Truth Tables

x x’
0 1
1 0
• AND gate gives high output if and only if all of its inputs
are high
• OR gate output is LOW if and only if all of its inputs are
LOW.
A B Q A B Q
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

NAND NOR
• NAND gate gives LOW output if and only if all of its
inputs are HIGH
• NOR gate output is HIGH if and only if all of its inputs
are LOW.
 Exclusive OR (XOR)

XOR gate output is HIGH if it has odd number of HIGH inputs.

 Sum-of-Products and Product-of-Sums Forms

If a function f is specified in the form of a truth table, then

an expression that realizes f can be obtained by considering
either the rows in the table for which f = 1, or by
considering the rows for which f = 0.
Minterms

For a function of n variables, a product term in which each

of the n variables appears once, either in uncomplemented
or complemented form is called a minterm.
For a given row of the truth table, the minterm is formed by
including xi if xi = 1 and by including xi’ if xi = 0.
 Sum-of-Products Form

Any function f can be represented by a sum of minterms that

correspond to the rows in the truth table for which f = 1.

Example:

f
A logic expression consisting of product (AND) terms
that are summed (ORed) is said to be in the sum-of
products (SOP) form. If each product term is a minterm,
then the expression is called a canonical sum-of-
products for the function f
Maxterms
• A function f can also be synthesized by considering
the rows for which f = 0.
• This alternative approach uses the complements of
minterms, which are called maxterms.
Product-of-Sums Form
• If a given function f is specified by a truth table,
then its complement f’ can be represented by a
sum of minterms for which f’ = 1, which are the
rows where f = 0.

Example:
If we complement this expression using
DeMorgan’s theorem, the result is
• A logic expression consisting of sum (OR) terms
that are the factors of a logical product
• (AND) is said to be of the product-of-sums (POS)
form.
• If each sum term is a maxterm, then the expression
is called a canonical product-of-sums for the given
function.
 Karnaugh map

• It is an alternative to the truth-table form for

representing a function. The map consists of cells that
correspond to the rows of the truth table.
• it allows easy recognition of minterms that can be
combined
Three-Variable Map
• Minterms in any two cells that are adjacent,
either in the same row or the same column, can
be combined.
• The adjacent cells must differ in the value of
only one variable.
• Thus the columns are identified by the
sequence of (x1, x2) values of 00, 01, 11, and
10.
• This makes the second and third columns different
only in variable x1. Also, the first and the fourth
columns differ only in variable x1, which means that
these columns can be considered as being adjacent. (A
sequence of codes, or valuations, where consecutive
codes differ in one variable only is known as the Gray
code.)
Four-Variable Map
 X1, x2
X3, x4 00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 1 1 1 0
10 1 1 0 1
Terminology

Some of the terminologies that are useful for describing the

minimization process are:

Literal
Each appearance of a variable, either
uncomplemented or complemented, in a logical term is
called a literal. For example, the product term x1x2x3
has three literals, and the sum term (x1’+x3+x4’+x6)
has four literals.
Implicant
A product term that indicates the input valuation(s) for
which a given function is equal to 1 is called an implicant of
the function. The most basic implicants are the minterms.
 Example:
f (x1, x2, x3) = ∑m(0, 1, 2, 3, 7).

• There are 11 implicants for this function:

• five minterms: x1’x2’x3’, x1’x2’x3,
x1’x2x3’, x1’x2x3, and x1x2x3.
• five implicants that correspond to all
possible pairs of minterms: x1’x2’ (m0
and m1), x1’x3’ (m0 and m2), x1’x3 (m1
and m3), x1’x2 (m2 and m3), and x2x3
(m3 and m7).
• one implicant that covers a group of four
minterms: x1’.
 Prime Implicant
An implicant is called a prime implicant if it cannot be
combined into another implicant that has fewer
literals.

Here there are two prime implicants: x1’

and x2x3.
Cover
A collection of implicants that account for all
valuations for which a given function is equal to 1 is
called a cover of that function.
A number of different covers exist for most
functions.
• A set of all minterms for which f = 1 is a cover.
• A set of all prime implicants is a cover.
 A cover defines a particular implementation of the
function.

While all of these expressions represent the function f

correctly, the cover consisting of prime implicants leads to the
lowest-cost implementation.
Cost
Cost of a logic circuit is the number of gates plus the total
number of inputs to all gates in the circuit.
If we assume that the input variables are available in both
true and complemented forms, then the cost of the
expression, is 9. Otherwise its cost is 13.
If an inversion is needed inside a circuit, then the
corresponding NOT gate and its input are included in the
cost. For example, the expression

has a cost of 14.

Essential Prime Implicant

If a prime implicant includes a minterm for which f = 1 that is not included in
any other prime implicant, then it is called an essential prime implicant.
 Minimization Procedure
Consider the following examples in which there is a choice as which
prime implicants to include in the final cover
• There are five prime implicants:
x1’x3, x2’x3, x3x4’, x2x3’x4,
x1’x2x4.
• The essential ones are x2’x3,
(because of m11), x3x4’ (because of
m14), x2x3’x4 (because of m13).
• They must be included in the cover.
These three prime implicants cover
all minterms for which f = 1 except
m7. It is clear that m7 can be
covered by either x1’x3 or x1’x2x4
 Because x1’x3 has a lower cost, it is chosen for the
cover. Therefore, the minimum-cost realization is

The process of finding a minimum-cost circuit involves the following

steps:
1. Generate all prime implicants for the given function f .
2. Find the set of essential prime implicants.
3. If the set of essential prime implicants covers all valuations for
which f = 1, then this set is the desired cover of f . Otherwise,
determine the nonessential prime implicants that should be added to
form a complete minimum-cost cover.
 Consider the following example:

only x3’x4’ is essential.

Then the best choice
to implement the
minimum cost circuit
is
Sometimes there may not be any essential prime implicants at all.
Example:

Two alternatives:
 Minimization of Product-of-Sums Forms
Example1:

OR
Its cost is greater than the cost of the equivalent SOP
implementation
SOP COST: 6 (assuming input variables are
available in both true and complemented forms)

POS COST: 9
Example2:

OR
Assuming that both the complemented and uncomplemented
versions of the input variables x1 to x4 are available,

SOP COST: 18

POS COST: 15

SOP and POS implementations of a given function may

or may not entail the same cost.
Incompletely Specified Functions

In digital systems it often happens that certain input

conditions can never occur. For example, suppose that x1
and x2 control two interlocked switches such that both
switches cannot be closed at the same time. Then the input
valuations (x1, x2) = 11 is guaranteed not to occur. Then
we say that (x1, x2) = 11 is a don’t-care condition,
meaning that a circuit with x1 and x2 as inputs can be
designed by ignoring this condition. A function that has
don’t-care condition(s) is said to be incompletely
specified.
NAND and NOR Implementation
 Multilevel Synthesis

Factoring

Fan-in Problem
No. of inputs that a gate can drive is called fan in
Factoring can be used to deal with the fan-in problem.
 Functional Decomposition

• Using factoring, multilevel circuits are used to deal with fan-in

limitations. However, such circuits may be preferable even if
fan-in is not a problem. In some cases the multilevel circuits may
reduce the cost of implementation. On the other hand, they
usually imply longer propagation delays, because they use
multiple stages of logic gates.
• Complexity of a logic circuit can often be reduced by
decomposing a two-level circuit into subcircuits, where one or
more subcircuits implement functions that may be used in
several places to construct the final circuit
Example 1
• Assuming that inputs
are available only in
their true form, this
expression has seven
gates and 18 inputs to
gates, for a total cost of
25.
• To perform functional
decomposition we need
to find one or more
subfunctions that depend
on only a subset of the
input variables.
Now let g(x3, x4) = x3’x4 + x3x4’ and observe that g’ =
x3’x4’ + x3x4. The decomposed function f can be written
as
f = x1g + x2g’