SYNTHESIS

M.POOJITHA
SYNTHESIS
Synthesis is a process of converting the RTL,VHD,HDL code into TECHNOLOGY
SPECIFIED Gate level Netlist.
It involves mapping the functionality specified in the RTL code to a library of standard cells, such as
NAND, NOR, XOR gates, etc., provided by the target technology.
INPUTS:
● RTL
● LIB
● LEF
● Floorplan DEF
● SDC
● UPF
OUTPUTS:
● SDC
● DEF
● Scan DEF (.def)
● UPF
Required Files for Synthesis:

To perform synthesis effectively, several files are essential:

● RTL Code: The RTL code serves as the input, written in hardware description

languages like Verilog or VHDL, which captures the desired behavior of the

design.

● Technology Libraries: These libraries provide a collection of standard cells,

gates, and other components specific to the target technology.

● Constraint File: The constraint file guides the synthesis tool, providing

additional information and specifications for optimizing the netlist generation. It

Why is Synthesis Required?

Synthesis is a crucial step in VLSI chip design for several reasons:

● Translation: It enables the transformation of RTL code, which captures the design's

functional behavior, into a gate-level representation that can be implemented in

hardware.

● Optimization: Synthesis optimizes the design for various metrics, such as area,

power consumption, and timing. By leveraging advanced algorithms, it improves the

performance and efficiency of the resulting netlist.

● Complexity Management: As chip designs grow increasingly complex, synthesis

BASIC FLOW OF SYNTHESIS
Synthesis Flow
TYPES OF SYNTHESIS
Logical synthesis: Logical synthesis process the HDL (Verilog or VHDL) design and
generates gate level netlist . During this process,the compiler optimizes the design
based on predefined constraints.

Physical Aware Synthesis : Physical aware synthesis requires additional floorplan DEF
contains physical information like IO ports placements,macro placement
information,blockages information.

Additionally ,we use RC co-efficient file as one of the inputs to compute a more accurate
wire delay values compared to the WLM(Wire Load Model)method.
ADVANTAGES OF PHYSICAL AWARE SYNTHESIS
● Better PPA( Power,Performance,Area).
● Better timing correlation with PNR.
● Better turnaround time (reduces the number of iterations).
● Improvement in power.
● PNR runtime also reduces because of lesser violations.
Logic Synthesis flow:
DIFFERENCE BETWEEN LOGIC AWARE SYNTHESIS AND
PHYSICAL AWARE SYNTHESIS:

Logic aware synthesis Physical Aware synthesis

INPUTS: RTL,UPF,Libraries ,Constraints INPUTS:

RTL,UPF,Libraries ,Constraints ,.tf(Technology
Files),TLU+ Files for RC Extraction , Floorplan DEF.

1. TO calculate the Net Delays Wire Load Models 1. TLU+ Files are used to calculate the Net delays
are used.

2. Uncertainty is More 2. Uncertainty is less.

3. PPA is not accurate compare to Physical aware 3. We use floor plan DEF as a input to get better PPA
Synthesis

4. Runtime is less compare to physical aware 4. Runtime is more compared to Logic aware synthesi
synthesis
DC Synthesis Flow
Library Objects:

● link_library
● target_library
● symbol_library
● synthetic_library
link_library: It used for linking the design . it contains the libraries that are used to
reference macros and other cells that are not synthesized by the the design compiler.
Target_library:It is used for Technology mapping.it contains the cells that are used to
synthesize the design. It contains the technology specific low level cells
(AND,OR,DEF,etc…)
symbol_library: It contains definitions of the graphic symbols that represent library
cells in the schematics.
● Semiconductor vendors maintain and distribute the symbol libraries.
● DC uses symbol libraries to generate the design schematic .
● Must use design vision to view the design schematic.

synthetic_library: It contains high level generic components such as adders,multipliers

etc…
Design Environment Parameters
● set_operating _conditions
● set_wire _load_model
● set_drive
● set_driving_cell
● Set_load
● set_fanout_load
● set_min_library
set_operating_conditions:The "set_operating_conditions"
command in synthesis is used to specify operating conditions
like best, typical, or worst case for analysis and optimization.
This command helps guide the optimization and mapping
process by setting goals such as timing and area through
constraints.
Operating conditions are crucial in logic synthesis as they
influence the synthesis optimization process and the final
design outcome.
set_wire_load_model:The process of setting the wire load model in synthesis
involves selecting a wire load model (WLM) to estimate the interconnect wire
delay during the pre-layout phase of the design cycle
In synthesis, the wire load model is used to calculate interconnect wiring delays,
resistance, capacitance, and area overhead due to interconnect. Different wire load
models are available in technology libraries, each representing specific block sizes
of logic.
The selection of a wire load model is typically based on the chip area of the block,
but these models can be customized according to user requirements.
Wire load models are essential for estimating the length, resistance, capacitance,
and area overhead of nets based on their fanouts and block sizes.
set_drive:The set_drive command is used in logic synthesis to
specify the external drive strength of input ports as a resistance value. It
models the drive resistance of the cell driving the input port.
Here are the key points about using set_drive:
● It is used to specify the drive strength of the input port by setting the
external drive resistance to the port. A value of 0 signifies the
highest drive strength.
● Example usage:
set_drive 0 {CLK RST}

This sets the drive strength of the CLK and RST input ports to the highest
value.
Set_driving_cell: It is typically used along with set_driving_cell
to model the drive resistance of the cell driving the input port.
● Example usage of set_driving_cell
● set_driving_cell -lib_cell BUFX4 -pin ZN [all_inputs]
● The set_drive and set_driving_cell commands help the
synthesis tool accurately estimate the timing and optimize the design.

So in summary, set_drive is a key constraint used in logic synthesis to

specify the drive strength of input ports, which helps the synthesis tool
perform timing-driven optimization and generate an accurate netlist.
set_load:The command set_load in synthesis is used to specify the capacitive load on output
ports or internal nets in the design. It is an important constraint that helps the synthesis tool
accurately model the delay and optimize the design accordingly.
Here are the key points about using set_load :
● It can be applied to output ports or internal nets in the design.
● The value specified is the capacitance in the unit of capacitance defined in the synthesis
constraints file.
● For output ports, it models the capacitive load driven by the output buffer.
● For internal nets, it models the capacitance of the fanout gates and interconnect.
Some example of set_load:
set_load 50 [all_outputs] # Set 50 units of capacitance on all outputs

set_load 0.1 [get_pins UFF0/Q] # Set 0.1 units on an internal pin

set_load -subtract_pin_load 0.025 [get_nets UCNT0/NET5] # Subtract pin cap from net
load
set_fanout_load:The "set_fanout_load" command in synthesis
tools like Synopsys Design Compiler is used to set the specified fanout
load on the output ports.
This command allows designers to define the load that an output port
can drive, influencing the design performance and characteristics.
By setting the fanout load, designers can optimize the design for factors
like area, speed, and power consumption based on their specific
requirements.
TIMING OPTIMIZATION TECHNIQUES

● Multibit Register grouping

● Constant flop propagation
● TNS driven placement
● Register _retiming
● Register _Duplication
● Prioritizing and enabling high effort timing opt
● Buffer aware placement
● Automatic timing control
● Via ladder supports
● Creating path groups by giving specific weightage and applying critical range.
Multi-bit Register Grouping

This technique involves the use of multi-bit flip-flops (MBFFs) to reduce power
consumption and improve timing in integrated circuit (IC) designs.
By clustering registers into MBFFs, clock circuitry can be shared, leading to a
reduction in the number of clock sinks and enhancing power optimization.
MBFFs offer benefits such as reduced clock tree length, which in turn decreases
clock-tree buffers and power consumption, ultimately improving design skew.
Additionally, MBFF merging mechanisms have been introduced to optimize
power consumption during the physical implementation stage of ICs,
demonstrating significant power reduction in clock tree networks while
maintaining good timing and routing convergence.
Constant flop Propagation

● Constant flop propagation in synthesis refers to the optimization technique

used by synthesis tools to minimize hardware implementation by identifying
and removing registers with constant values that are not required in the design.
● This process involves automatically removing flip-flops that hold constant
values, such as zeros, to streamline the design and improve efficiency.
● By eliminating these unnecessary elements, constant flop propagation helps
optimize the design for performance, power consumption, and area utilization
during the RTL synthesis stage of digital chip design.
TNS Driven Placement
● The concept of total negative slack in driven placement during synthesis involves addressing
timing issues in chip design.
● It is crucial for ensuring that the design meets timing constraints. To resolve total negative slack
during synthesis, a method involves incrementally transforming the structure of individual circuits
while maintaining logical functionality to eliminate negative slacks
● This process includes steps like floorplanning, global placement, and incremental transformation
of circuit structures. Additionally, the flow uses slack values to determine which gates or nets
need optimization, with a constant slack threshold and target slack set by the user.
● The workflow for troubleshooting and resolving total negative slack involves analyzing the
reasons for the failures, such as excessive logic levels, fast clocks, or high fanout, and making
adjustments like pipelining paths or adjusting clock rates to meet timing requirements.
Register_retiming
● Register retiming in synthesis involves an optimization technique that allows for the
movement of registers across combinatorial logic to enhance circuit performance without
altering the functionality at primary input/output ports.

● This process is crucial for improving timing and balancing delays within a design. Register
retiming can be performed using tools like Precision Synthesis, which offers algorithms to
move registers forward or backward to address negative path slack.

● Register retiming is particularly beneficial for FPGA designs, enabling the adjustment of
register locations to equalize delays and optimize clock period and area. This technique is
instrumental in managing routing delay issues and enhancing the performance of complex
FPGA designs by strategically placing sequential elements to minimize path delays.
Register_duplication
Register duplication is a synthesis optimization technique used to reduce the fan-out of registers and improve
timing performance. It involves creating multiple copies of a register to drive different destinations, reducing
the number of loads on each copy.

Synthesis tools typically provide options to control register duplication:

● Maximum Fan-Out assignment: Specifies the maximum number of destinations a register can drive
before being duplicated
● Manual Logic Duplication: Allows manually duplicating specific registers to optimize timi
Register duplication can help in the following scenarios:

● Registered output signals used internally with high fan-out

● Flops driving many loads, causing timing issues
● Designs with a significant amount of math function
In summary, register duplication is a powerful synthesis technique to optimize timing by reducing fan-out, but
should be used judiciously considering its impact on resources and compilation time.
Prioritizing and Enabling High Effort Timing Opt
● To prioritize and enable high-effort timing optimization in synthesis, it is crucial to
focus on techniques that enhance timing performance while considering factors
like area and power constraints.
● By utilizing task-based parallel programming, one can achieve efficient timing
optimization without compromising quality of results.
● Techniques such as retiming of sequential cells, critical path resynthesis, and area
optimization play a significant role in improving design timing and reducing delay
violations.
Additionally, modifying the floorplan at the block level can help reduce congestion and
timing violations, ensuring optimal placement and routing of design elements.
Buffer Aware Placement

The concept of buffer aware placement in synthesis involves strategically placing buffers in
VLSI circuits to optimize performance, reduce power consumption, and address timing issues.

This technique is crucial in modern circuit design due to the increasing dominance of
interconnect delays over gate delays as technology scales down. Buffer insertion is essential for
achieving timing objectives and fixing electrical violations in interconnects.

Tools like physical synthesis play a key role in this process by optimizing placement, timing,
power consumption, and crosstalk effects in integrated circuit designs.

Overall, buffer aware placement in synthesis is a critical aspect of VLSI circuit design, ensuring
efficient signal propagation, reduced power consumption, and enhanced timing characteristics in
modern integrated circuits.
Automatic timing control
● Automatic timing control in synthesis involves the automated synthesis of
controllers for timed systems, where algorithms are used to find winning
strategies for certain games.
● This process focuses on the optimization problem defined over an infinite
prediction/control horizon, addressing issues related to discrete-time hybrid
systems and nonlinear systems that require specific smoothness
assumptions.
● The aim is to develop efficient algorithmic implementations that provide
exact solutions to optimal control problems for constrained or hybrid
systems.
Via ladder support

● Via ladder support is a stacked via that starts from the pin
layer and extends into an upper layer where the router
connects to it.
● Via ladder reduces the via resistance which can improve
the performance and Electromigration robustness.
● The tool can automatically insert the via ladder for cell
pins on timing critical paths.
Creating path groups by giving specific weightage and applying critical
range

Tocreate path groups with specific weightage and critical range in synthesis, you can use the
group_path command in Design Compiler. Here's how it works:
group_path -name <group_name> -weight <weight_value> -critical_range <range_value> -from
<from_list> -to <to_list>
● group_name: Specifies the name of the path group you want to create
● weight_value: Assigns a weight to the path group. The violations are multiplied by this
weight to determine the cost. A higher weight means the paths in this group will be optimized
more aggressively. The value can range from 0 to 100, with 1 being the default.
● range_value: Specifies the critical range. All paths in the group whose timing violation is
within this range of the worst violator will be optimized, not just the worst violator. This can
improve results at the cost of longer compile times.
● from_list: Specifies the start points of the paths to include in the group
● to_list: Specifies the endpoints of the paths to include in the group.