BEHAVIORAL

DESCRIPTION IN
VERILOG HDL
PRESENTED BY:
NAVEENA.M - 2023236031
M.E – VLSI DESIGN (I YEAR)
CONTENT
• BEHAVIORAL MODELING
• Learning Objectives
• Structured Procedure blocks-blocking and non-
blocking
• Timing Controls
• Conditional Statements
• Multiway Branching
• Sequential and Parallel Blocks
• Generate Blocks
• EX. Behavioral 4-to-1 Multiplexer.
BEHAVIORAL MODELING:
• Behavioral modeling represents the circuit at a very
high level of abstraction.
• Design at this level resembles C programming more
than it resembles digital circuit design.
• Behavioral Verilog constructs are similar to C
language constructs in many ways.
• Verilog is rich in behavioral constructs that provide
the designer with a great amount of flexibility.
Learning Objectives:
• Explain the significance of structured procedures always and initial in
behavioral modeling.
• Define blocking and nonblocking procedural assignments.
• Understand delay-based timing control mechanism in behavioral
modeling. Use regular delays, intra-assignment delays, and zero delays.
• Describe event-based timing control mechanism in behavioral modeling.
Use regular event control, named event control, and event OR control.
• Use level-sensitive timing control mechanism in behavioral modeling.
• Explain conditional statements using if and else.
• Describe multiway branching, using case, casex, and casez statements.
• Understand looping statements such as while, for, repeat, and forever.
• Define sequential and parallel blocks.
• Understand naming of blocks and disabling of named blocks.
• Use behavioral modeling statements in practical examples
Structured Procedure blocks

• Verilog provides two structured procedures.

1. initial statement
2. Always statement
 initial statement:
 All statements inside an initial statement constitute an initial
block. An initial block starts at time 0, executes exactly once
during a simulation, and then does not execute again.
 If there are multiple initial blocks, each block starts to
execute concurrently at time 0. Each block finishes execution
independently of other blocks.
 the three initial statements start to execute in parallel at
time 0. If a delay # is seen before a statement, the statement
is executed time units after the current simulation time.
Example of initial Statement
module stimulus;
reg x,y, a,b, m;
Initial
m = 1'b0; //single statement; does not need to be grouped
Initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0; end
initial
Begin
#10 x = 1'b0;
#25 y = 1'b1;
end initial
#50 $finish;
endmodule
Always statement:

• All behavioral statements inside an always

statement constitute an always block. The always
statement starts at time 0 and executes the
statements in the always block continuously in a
looping fashion.
• This statement is used to model a block of activity
that is repeated continuously in a digital circuit.
• An example is a clock generator module that
toggles the clock signal every half cycle. In real
circuits, the clock generator is active from time 0 to
as long as the circuit is powered on.
• If there is no $stop or $finish statement to halt the
simulation, the clock generator will run forever.
Example of always Statement:
module clock_gen (output reg clock);
//Initialize clock at time zero
initial
clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always
#10 clock = ~clock;
Initial
#1000 $finish;
endmodule
Procedural Assignments
• Procedural assignments update values of reg,
integer, real, or time variables.
• Syntax:
assignment ::= variable_lvalue =
[delay_or_event_control ] expression
• The left-hand side of a procedural assignment can
be one of the following:
• A reg, integer, real, or time register variable or a
memory element
• A bit select of these variables (e.g., addr[0])
• A part select of these variables (e.g., addr[31:16]
Types:
1. blocking and
2. nonblocking.
Blocking Assignments:
• Blocking assignment statements are executed in the
order they are specified in a sequential block.
• A blocking assignment will not block execution of
statements that follow in a parallel block.
Example of Blocking Statements:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
Begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z} //Assign result of concatenation to // part
select of a vector
count = count + 1; //Assignment to an integer (increment)
end
Nonblocking Assignments:
• Nonblocking assignments allow scheduling of
assignments without blocking execution of the
statements that follow in a sequential block.
• A <= operator is used to specify nonblocking
assignments. Note that this operator has the same
symbol as a relational operator,
less_than_equal_to.
Ex. of Nonblocking Assignments:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //Initialize vectors
reg_a[2] <= #15 1'b1; //Bit select assignment with delay
reg_b[15:13] <= #10 {x, y, z};
//Assign result of concatenation //to part select of a vector
count <= count + 1; //Assignment to an integer (increment)
end
Example of Nonblocking Statements:
//Illustration 1: Two concurrent always blocks with blocking
//statements
always @(posedge clock)
a = b;
always @(posedge clock)
b = a;
//Illustration 2: Two concurrent always blocks with nonblocking
//statements
always @(posedge clock)
a <= b;
always @(posedge clock)
b <= a;
Timing Controls:
• Various behavioral timing control constructs are
available in Verilog.
• In Verilog, if there are no timing control statements,
the simulation time does not advance.
• Timing controls provide a way to specify the
simulation time at which procedural statements will
execute.
• There are three methods of timing control:
1. delay-based timing control,
2. event-based timing control, and
3. level-sensitive timing control.
1.Delay-based timing control:
• Delay-based timing control in an expression
specifies the time duration between when the
statement is encountered and when it is executed.
• Delay-based timing control can be specified by a
number, identifier, or a mintypmax_expression.
• There are three types of delay control for
procedural assignments:
I. regular delay control,
II. intra-assignment delay control, and
III. zero delay control.
I. Regular delay control:
Regular delay control is used when a non-zero delay is
specified to the left of a procedural assignment.
ll.Intra-assignment delay control:
Instead of specifying delay control to the left of the
assignment, it is possible to assign a delay to the right of the
assignment operator. Such delay specification alters the
flow of activity in a different manner.
lll. Zero delay control :
The order of execution of different always-initial blocks is
nondeterministic.
Zero delay control is a method to ensure that a statement is
executed last, after all other statements in that simulation
time are executed. This is used to eliminate race conditions.
2.Event-Based Timing Control:
• An event is the change in the value on a register or a net. Events
can be utilized to trigger execution of a statement or a block of
statements.
• There are four types of event-based timing control:
 regular event control- @ symbol is used to specify an event
control. Statements can be executed on changes in signal value
or at a positive or negative transition of the signal value.
 named event control- . An event is triggered by the symbol ->.
The triggering of the event is recognized by the symbol @.
 event OR control- Sensitivity lists can also be specified using the
"," (comma) operator
 level-sensitive timing control- to wait for a certain condition to
be true before a statement or a block of statements is executed.
The keyword wait is used for level-sensitive constructs.
Conditional Statements:
• Conditional statements are used for making decisions based upon
certain conditions.
• These conditions are used to decide whether or not a statement
should be executed. Keywords if and else are used for conditional
statements. There are three types of conditional statements.
//Type 1 conditional statement. No else statement. //Statement
executes or does not execute.
if () true_statement ;
//Type 2 conditional statement. One else statement //Either
true_statement or false_statement is evaluated if () true_statement ;
else false_statement ;
//Type 3 conditional statement. Nested if-else-if. //Choice of multiple
statements. Only one is executed. if () true_statement1 ; else if ()
true_statement2 ;
else if () true_statement3 ;
else default_statement ;
Multiway Branching:
• The nested if-else-if can become unwieldy if there are too many
alternatives. A shortcut to achieve the same result is to use the case
statement.
1.case Statement:
• The keywords case, endcase, and default are used in the case
statement.
• Example :
//Execute statements based on the ALU control signal
reg [1:0] alu_control; …… …….
case (alu_control)
2'd0 : y = x + z;
2'd1 : y = x - z;
2'd2 : y = x * z;
default : $display("Invalid ALU control signal");
endcase
2. casex, casez Keywords :
• casez treats all z values in the case alternatives or the case
expression as don't cares. All bit positions with z can also
represented by ? in that position.
• casex treats all x and z values in the case item or the case
expression as don't cares.
Example casex Use:
reg [3:0] encoding;
integer state;
casex (encoding) //logic value x represents a don't care bit.
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
default : next_state = 0;
endcase
Thus, an input encoding = 4'b10xz would cause next_state = 3 to
be executed.
Loops:
• There are four types of looping statements in
Verilog:
• while, for, repeat, and forever. The syntax of these
loops is very similar to the syntax of loops in the C
programming language.
• All looping statements can appear only inside an
initial or always block. Loops may contain delay
expre
1. While- The while loop executes until the while
expression is not true. If the loop is entered when
the while-expression is not true, the loop is not
executed at all.
2. For Loop:
• The keyword for is used to specify this loop.
• The for loop contains three parts:
 An initial condition
A check to see if the terminating condition is true
 A procedural assignment to change value of the
control variable.
3. Repeat Loop:
The repeat construct executes the loop a fixed number
of times.
A repeat construct cannot be used to loop on a general
logical expression. A repeat construct must contain a
number, which can be a constant, a variable or a signal
value
4. Forever loop :
• A forever loop is typically used in conjunction with
timing control constructs. If timing control
constructs are not used,
• the Verilog simulator would execute this statement
infinitely without advancing simulation time and
the rest of the design would never be executed.
Sequential and Parallel Blocks:
1.Block types:
Sequential blocks:
• The keywords begin and end are used to group
statements into sequential blocks. Sequential blocks
have the following characteristics:
• The statements in a sequential block are processed
in the order they are specified. A statement is
executed only after its preceding statement completes
execution (except for nonblocking assignments with
intra-assignment timing control).
• If delay or event control is specified, it is relative to
the simulation time when the previous statement in
the block completed execution.
Example of Sequential Blocks:
//Illustration 1: Sequential block without delay
reg x, y;
reg [1:0] z, w;
initial begin
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
end
//Illustration 2: Sequential blocks with delay.
reg x, y;
reg [1:0] z, w;
initial
begin
x = 1'b0; //completes at simulation time 0
#5 y = 1'b1; //completes at simulation time 5
#10 z = {x, y}; //completes at simulation time 15
#20 w = {y, x}; //completes at simulation time 35
end
ll.Parallel blocks:
Parallel blocks, specified by keywords fork and join,
provide interesting simulation features. Parallel
blocks have the following characteristics:
• Statements in a parallel block are executed
concurrently.
• Ordering of statements is controlled by the delay or
event control assigned to each statement.
• If delay or event control is specified, it is relative to
the time the block was entered
2.Special Features of Blocks
l.Nested blocks:
• Blocks can be nested.
• Sequential and parallel blocks can be mixed.
ll.Named blocks:
Blocks can be given names.
• Local variables can be declared for the named block.
• Named blocks are a part of the design hierarchy.
Variables in a named block can be accessed by using
hierarchical name referencing.
• Named blocks can be disabled, i.e., their execution can
be stopped.
lll. Disabling named blocks
• The keyword disable provides a way to terminate
the execution of a named block.
• disable can be used to get out of loops, handle
error conditions, or control execution of pieces of
code, based on a control signal.
Generate Blocks:
• Generate statements allow control over the
declaration of variables, functions, and tasks, as
well as control over instantiations.
• Generated instantiations can be one or more of the
following types:
 Modules
 User defined primitives
 Verilog gate primitives
 Continuous assignments
 initial and always blocks
Three methods to create generate statements:
• Generate loop
• Generate conditional
• Generate case
EX. Behavioral 4-to-1 Multiplexer:

// 4-to-1 multiplexer. Port list is taken exactly from

// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
//output declared as register
reg out;
//recompute the signal out if any input signal changes. //All input signals that cause a
recomputation of out to //occur must go into the always @(...) sensitivity list. always @(s1 or s0 or i0
or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
EX.2:Traffic light Controller
TESTBENCH:
Simulation:
THANK YOU
REFERENCE:
• Verilog HDL Book by Samir Palnitkar,foreword by
Prabhu goel.-2^nd Edition in 7^ th topic ………
Behavioral modeling…and simulation code get from
github.com on traffic light controller using Verilog
code.