System design using

Verilog
AP3251 ADVANCED DIGITAL SYSTEM DESIGN
PRESENTED BY BALAJI PRITHVIRAJ N (2023203035)
Contents
•HDL based synthesis
•Synthesis of finite state machine
•Structural modelling
•Conclusion
•References
FPGA design flow
HDL based synthesis
Introduction:
•Synthesis is a process in which the digital design that is modeled using HDL is
translated into an implementation consisting of logic gates.
•It will make an optimal design based on the working strategy which we are using
and also give the consumption of resources as available.
What is logic synthesis?
•Logic synthesis is the process of converting a high – level description of the
design into an optimized gate-level representation , given a standard cell library
and certain design constraints.
•A standard cell library can have simple cells such as basic logic gates like
AND,OR and NOR,adders,muxes and etc.
•A standard cell library is also know as the technology library
Contd.
•The designer would first
understand the architectural
description. Then he would
consider design constraints
such as timing , area ,
testability and power.
•The designer partitions the
design into higher level blocks
and draw them on a paper and
describe the functionality of a
circuit. This is the high level
description.
Contd.
•The higher level description is fed to the computer – aided logic synthesis tool,
which performs several iterations internally and generates the optimized gate-
level description.
•Verilog HDL has become one of the popular HDLs for the writing of higher-level
descriptions.
•Automated logic synthesis has significantly reduced time for conversion from
high-level design representation to gates.
•This has allowed designers to spend more time on designing at a higher level of
representation, because less time is required for converting the design to gates.
Impact of Logical synthesis
•For large designs, manual conversion was prone to human error. A small gate missed
somewhere could mean redesign of entire blocks.
•The designer could never be sure that the design constraints were going to be met until
the gate level implementation was completed and tested.
•A significant portion of the design cycle was dominated by the time taken to convert a
high level design into gates.
•What-if scenarios were hard to verify. For example , the designer designed a block in
gates that could run at a cycle time of 20 ns. If the designer wanted to find out whether
the circuit could be optimized to run faster at 15 ns, the entire block had to be
redesigned. Thus, redesigned was needed to verify what-if scenarios.
•If a bug was found in the final gate-level design, this would sometimes require design of
thousands of gates.
Verilog HDL synthesis
•For the purpose of logic synthesis, designs are currently written in an HDL at a
register transfer level(RTL).
•RTL is used for an HDL description style that utilizes a combination of data flow
and behavioral constructs.
•Logic synthesis tools like Xilinx take the RTL HDL description and convert it to
an optimized gate-level netlist.
Verilog constructs
Construct Type Keyword or Description Notes
Ports Input, output, inout
Parameters Parameters
Module definition module
Signals and variables Wire, reg Vectors are allowed
Instantiation Module instantiation E.g. mymux(out,i0,i1,s)
Functions Functions and tasks
Procedural Always, if , then , else , case ,
casex , casez
Data flow Assign
Loops For,while,forever @(posedge clk) or always @ *
 RTL design flow from RTL to gates
• RTL description: The designer describes the design at a high level by using RTL constructs. After the
functionality is verified , the RTL description is input to the logic synthesis tool.
• Translation: The RTL description is converted by logic synthesis tool to an unoptimized, intermediate,
internal representation. This process is called translation , it is a simple process composed of a few Verilog
constructs.
• Logic optimization: The logic is now optimized to remove redundant logic. Various technology
independent Boolean logic optimization techniques are used.
• Technology mapping and optimization: In this step, the synthesis tool takes the internal representation in
GATES, using the cells provided in the technology library.
• Design constraints:
• Timing? The circuit must meet timing requirements. An internal static timing analyzer checks timing
• Area? The area of the final layout must not exceed a limit.
• Power? The power dissipation in the circuit must not exceed a threshold.
Contd.
•Optimized gate-level description: After the technology mapping is complete,
an optimized gate level netlist described in terms of target technology
components is produced.
Synthesis of FSM
Introduction: An FSM has finite number of states , an input which triggers
transition between states and an output.
How to write Verilog code for FSM?
Structural modelling in Verilog
Introduction:
•Structural refers to describing a design using module instances (especially low
level building blocks like AND,OR,MUX,ADDER,FLIP FLOP etc.)
•Structural model is a module that instantiates other module and Verilog
primitives(and, or ,nand , nor etc.)
Contd.
•Modules are instances of hardware
•Here functions are defined using basic components such as inverter, MUX, adder, decoder, basic
digital logic gates etc. It is just like connecting and rearranging different parts of circuit.
Implemented using function.
•Used to design bigger circuits or complex logic
•After switch level modeling, structural modeling is the lowest level of abstraction in Verilog. It is
also called as gate level modeling because we only describe a hardware in logic gates and their
interconnections
Keywords required: and(),or(), not(), nor(), nand(), wire, xor(), xnor()
•In above keywords of logic gates, inside the parentheses we are required to list input and output
connections. In all of the above logic gate keywords, first list will be output and rest will be
inputs. For example and(y,a,b); instantiate a AND gate with output y and inputs a,b.
Contd.
•Using wire keyword, you can make internal connections between the logic gates.
To make internal connections, we are required to declare the internal wire name.
For example wire x; will declare a wire which has name x.
Describe a hardware using keywords
Let us describe a 2X1 MUX using structural modeling. Write the Boolean expression and make a
logic circuit diagram.
Boolean expression: Y = SI0+SI1
Circuit diagram:
Let's describe 2X1 MUX in Verilog
First, create a module and define input output ports. Make logic gates by instantiating respective logic gate
keyword. There is two AND gate, one OR gate and one NOT gate.
/*
Module : mux2x1_struct.v
Created By : circuitfever.com
Create on : 22-01-2023
*/
module mux2x1(
input I0,I1,S,
output Y
);

not();
and();
and();
or();
endmodule
contd
Declare internal connection using wire keyword
/*

Module : mux2x1_struct.v
Created By : circuitfever.com
Create on : 22-01-2023
*/
module mux2x1(
input I0,I1,S,
output Y
);
wire w1,w2,w3;
not();
and();
and();
or();
endmodule
Contd.
Now make connection between logic gates and input output ports.
/*

Module : mux2x1_struct.v
Created By : circuitfever.com
Create on : 22-01-2023
*/
module mux2x1(
input I0,I1,S,
output Y
);
wire w1,w2,w3;
not(w1,S);
and(w2,I0,w1);
and(w3,I1,S);
or(Y,w2,w3);
endmodule
References
•Samir palnitkar – Verilog HDL – Prentice Hall (1996)
•https://circuitfever.com/structural-modeling-in-verilog
THANK YOU!