1.

3 FUNCTIONAL PIN
DIGARAM
8086 PIN CONFIGURATION

2
 Operates in 3 Modes
• Minimum Mode
• Maximum Mode
• Min-Max Mode

3
 INTEL 8086 - Pin Details

Power Supply
5V  10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
Clock minimum 4
clks
4
 Power supply – Pin number 40
• It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.
 GND Ground – Pin number 1 and 20
• These two pins acts as the ground. This pin directs the extra current of the
microprocessor to ground.
 CLK Clock signal – Pin number 19
• Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and
10MHz.
 RESET – Pin number 21
• It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4
clock cycles to RESET the microprocessor.

5
 INTEL 8086 - Pin Details

Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.

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 Address/data bus- Pin number 2 to 16 and 39
• AD0-AD15. These are 16 address/data bus which are Multiplexed.AD0-AD7 carries
low order byte data and AD8AD15 carries higher order byte data.
• Total Address bus is of 20-bits
• Total Data bus is of16-bits
 ALE (Address Latch Enable ) – Pin number 25
• It is available at pin 25. A positive pulse is generated each time the processor begins
any operation. This signal indicates the availability of a valid address on the
address/data lines.
INTEL 8086 - Pin Details

Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3

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 Address/status bus -
• A16-A19/S3-S6. These are the 4 address/status buses.
• During the first clock cycle, it carries 4-bit address and later it carries status signals.
 NMI - Pin number 17
• Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt.
• This type of interrupt whenever occurred it directly get executed.
• These are basically uncontrollable interrupts generated inside the processor. When an
NMI occurs, then an interrupt service routine is generated by the interrupt vector table.
 INTR – Pin number 18
• INTR stands for an interrupt request. It checks the availability of pending interrupts in
queue.
• The processor after each clock cycle samples the INTR and if the signal at this pin is
found to be high then the processor controls that interrupt internally.
 NTA’ – Pin number 24
• It is an interrupt acknowledge pin. Whenever an INTR signal is generated, then the
microprocessor generates INTA signal, as a response to that interrupt and send
acknowledge to INTR. 9
 INTEL 8086 - Pin Details

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request
10
INTEL 8086 - Pin Details

Direct
Memory
Access

Hold

Hold
acknowledge

11
 HOLD – Pin number 31
• When an external device enables this pin then the processor stops accessing the buses
immediately after the recent task gets over.
• The master request for access through buses to stop the execution.
 HLDA – Pin number 30
• This pin is used as a response pin for the hold request.
• Once request for accessing the buses is produced by an external entity. Then the
microprocessor acknowledges the device that its request will be considered once it gets
over by the current operation.

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 INTEL 8086 - Pin Details

BHE#, A0: Bus High Enable/S7

0,0: Whole word Enables most
(16-bits)
significant data bits
0,1: High byte D15 – D8 during read
to/from odd address or write operation.
1,0: Low byte S7: Always 1.
to/from even address

1,1: No selection

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 BHE’ / S7 Bus High Enable – Pin number 34
• The combination of the BHE signal and S7 status informs about the existence of the data
on the bus. Also, different combinations show whether the bus is containing overall 16
bit, upper byte or lower byte of the data.

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 INTEL 8086 - Pin Details

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins

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 MN/MX’ – Pin number 33
• The status at this particular pin shows whether the processor is operating in the minimum
mode or maximum mode.
• A signal 0 at this pin informs that the 8086 is operating in maximum mode i.e., multiple
processors. While signal 1 shows the operation under minimum mode i.e., single
processor.

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Minimum Mode- Pin Details

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• RD’ – Pin number 32 – An active low signal at this pin shows that the microprocessor is
performing read operation with either memory or I/O devices\
• WR’ – Pin number 29 – An active low signal at this pin indicates that the processor is
performing write operation from either memory or I/O devices.
 M/IO’ – Pin number 28
• This pin indicates whether the processor is performing an operation with memory or I/O
devices. Whenever a high is present at this pin then it shows the operation is carried out
through the memory. While a low signal shows operation through I/O devices.
 DT/R’ – Pin number 27
• This pin is used to show whether the data is getting transmitted or is received. A high
signal at this pin provides the information regarding the transmission of data. While a low
indicates reception of data.
 DEN’ – Pin number 26
• DEN is used for data enable. This is an active low pin that means whenever a 0 is present
at this pin then the transceiver gets enabled and it separates the data from the multiplexed
address and data bus.

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 Maximum Mode - Pin Details

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.

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 S0‘, S1‘ and S2‘ – Pin number 26 to 28
• These are basically 3 status pins and are active low. This means that if the status at all
the 3 pins is 0 then it shows that multiple interrupts are to be handled in maximum
mode.

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 Maximum Mode - Pin Details

Lock Output
Used to lock buses

DMA
Request/Grant
Used through
local masters

Lock Output

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 RQ’/ GT0‘ and RQ’/ GT1‘ – Pin number 30 and 31
• Due to the involvement of multiple processors, these pins indicate the
request and grant permission for accessing the buses, memory and
peripherals.
 LOCK’ – Pin number 29
• This pin is involved in maximum mode operation. So, basically, when
a single processor is accessing the buses and peripherals then it locks
the resources being used by it. So, that no other entity can access it
until the recent processor frees it.
 QS0 and QS1 – Pin number 24 and 25
• These two pins indicate the status of the 6-byte pre-fetch queue
present in the architecture of 8086.

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 Maximum Mode - Pin Details

QS1 QS0
00: Queue is idle
01: First byte in queue
10: Queue is empty
11: show Subsequence
byte in queue
Queue Status
Work as(FIFO)

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 TEST – Pin number 23
• This pin basically shows the wait instruction. Whenever a low signal at
this pin occurs then the processing inside the processor continues. As
against, in case of the high signal, the processor has to wait for the
disabling of this pin.
 READY – Pin number 22
• This signal is used by the peripherals and memory devices in order to
show the readiness for the next operation.

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