5.

3 Integer and Floating –Point

Pipelining Stages
 INTEGER PIPELINING STAGES
• The Pentium is a superscalar processor and it has two integer pipelines, called U and
V. The process of issuing two instructions in parallel is known as pairing.
• The U-pipeline is able to handle the full instruction set of the Pentium but the V-
pipeline has limited handling capability.
• The V-pipeline is able to handle only simple instructions without any microcode
support.
• The V-pipeline is used to execute ‘simple integer instructions’ such as load/store type
instructions and the FPU instruction FXCH, but the U-pipeline executes any legitimate
Pentium instructions.
• Actually, Architecture of Pentium Processor use a set of pairing rules to select a
simple instruction which can go through the V pipeline.
• When instructions are paired, initially the instruction is issued to the U-pipe and then
the next sequential instruction is issued to the V-pipe.
• There are two integer pipelines and a floating-point unit in
the Architecture of Pentium Processor. Figure 12.3 shows
an integer pipeline. Each integer unit has the basic five-
stage pipeline as given below:
I. Pre-fetch (PF)
II. Decode-1 (D1)
III. Decode-2 (D2)
IV. Execute (E)
V. Write Back (WB)
Pre-fetch (PF)-
• In the pre-fetch stage of integer pipeline of the Pentium processor, instructions are fetched from the
instruction cache as instructions are stored initially in the instruction cache.
• After fetching, the CPU aligns the codes properly. As the instructions are of variable lengths, the initial
opcode bytes of each instruction must be properly aligned.
• After completion of the pre-fetch stage, the decode stages D1 and D2 will be executed.
Decode-1 (D1)
• In the decode-1 (D1) pipeline stage, the CPU decodes the instruction and generates a control
word(Pause, Stop, Start, Move Commands) . The D1 pipeline stage has two parallel instruction
decoders.
• These implement the pairing rules. Only a single control word may be sufficient to start execution of the
data transfer, arithmetic and logical operations .
• Basic functions - Checking Pairability of Instruction, Branch Prediction, Instruction Boundary
Information to Code Cache.
Decode-2 (D2)
• The decode-2(D2) pipeline stage is required whenever the control word from D1 stage is decoded to
complete the instruction decoding.
• In this stage, the CPU generates addresses for data memory.
Execute (EX)
• The execution stage is used for both ALU operations and data cache access.
• The data cache is used for data operands and ALU performs arithmetic logic computations or
floating-point operations.
• In the execution stage, all U-pipe and V-pipe instructions, except conditional branches, are verified
for correct branch prediction.
• A micro-code is designed to use both the U and V pipes. Therefore, microcode instructions are
executed faster on the Pentium than on the 80486.
Write Back (WB)
• The final stage of the five-stage pipeline is Write Back (WB).
• In the WB stage, the CPU updates the contents of registers and status of the flag register after
completion of execution.
• In this stage, the V-pipeline conditional branch instructions are verified for correct branch
prediction.
• The Pentium pipeline structure is similar to 80486 pipeline structure. Usually, the 80486 takes two
clock cycles to decode instructions, but the Pentium processor takes only one clock cycle as Pentium
processor has an additional integrating hardware in each pipeline stages to speed up the process
 FLOATING-POINT PIPELINE STAGES
• The 80486DX CPU is the first processor in which the 80387 math co-processor has been
incorporated on-chip to reduce the communication overhead.
• The 80486 CPU contains a floating-point unit, but this floating-point unit is not pipelined. The
Architecture of Pentium Processor has been designed for incorporating on the chip numeric data
processor.
• The Floating-Point Unit (FPU) of Pentium has an eight-stage pipeline
I. Pre-fetch (PF)
II. Decode-1 (D1)
III. Decode-2 (D2)
IV. Execute (dispatch)
V. Floating Point Execute-1 (X1)
VI. Floating Point Execute-2 (X2)
VII. Write Float (WF)
VIII. Error Reporting (ER)
• The first five stages of the pipeline are similar to the U and V integer pipelines. During the
operand fetch stage, the FPU fetches the operands either from the floating-point register or
from the data cache.
• The float­ing-point unit has eight general-purpose floating point registers. There are two
execution stages in Pentium such as the first execution stage (X1 stage) and the second
execution stage (X2 stage).
• In the X1 and X2 stages, the floating-point unit reads the data from the data cache and
executes the floating-point calculation.
Pre-fetch (PF)
• The pre-fetch stage is same as the integer pipeline of Pentium processor.
Decode-1 (D1)
• The decode-1 (D1) pipeline stage is also same as the integer pipeline of Pentium processor.
Decode-2 (D2)
• The decode-2 (D2) pipeline stage is worked as required whenever the control word from D1
stage is decoded to complete the instruction decoding.
• In this stage, it is the integer pipeline of Pentium processor.
Execution (EX)
• During the execution stage (E), the floating-point unit accesses the data cache and the floating-point
register to fetch operands. Before writing the floating-point data to the data cache, the floating-point
unit converts internal data format into appropriate memory representation format.
Floating Point Execute-1 (X1)
• In the Floating Point Execute-1 (X1) stage, the floating-point unit executes the first steps of the
floating-point calculations.
• While reading the floating-point data from the data cache, the floating-point unit writes the data into
the floating-point register.
Floating Point Execute-2 (X2)
• During the Floating Point Execute-2 (X2) stage, the Floating Point unit execute the remaining steps of
the floating-point computations.
Write Float (WF)
• In the Write Float (WF) stage, the floating-point unit completes the execution of the floating-point
calculations and then writes the computed result into the floating-point register file.
Error Reporting (ER)
• In the error reporting(ER) stage, the floating-point unit generates a report about the internal special
situations and updates the floating point status.
 Floating Point Instruction Paring

• The floating-point unit of Pentium consists of a dedicated adder, multiplier and

division units. All inde­pendent circuits are used to perform addition,
multiplication, division and other mathematical operations within very few clock
cycles.
• Floating-point Adder Segment (FADD)
• Floating-point Multiplier Segment (FMUL)
• Floating-point Exponent Segment (FEXP)
• Floating-point Rounder Segment (FRD)
Floating-point Adder Segment (FADD)
• The floating-point adder segment is used for addition of floating- point numbers and
execution of floating-point instructions such as addition, subtraction and comparison.
Floating-point Multiplier Segment (FMUL)
• The floating-point multiplier segment executes floating-point multiplication in single-
precision, double-precision and extended precision modes.
Floating-point Divider Segment (FDIV)
• This segment performs the floating-point division and executes square-root instructions.
Floating-point Exponent Segment (FEXP)
• The floating-point exponent segment calculates the floating-point exponent.
Floating-point Rounder Segment (FRD)
• After the floating-point addition or division operations, it is required to round off the
computed results before write back to the floating-point registers.
• The floating-point rounder segment is used to perform the round-off operation before
write-back stage.