|| Jai Sri Gurudev ||

Sri Adichunchanagiri Shikshana Trust

(R)

SJB Institute of Technology

Department of Electronics & Communication Engineering

VLSI Design – 18EC72

MODULE - 1

By
Chetana R
Assistant Professor
Dept of ECE, SJBIT
Chetana R, Associate Professor, Dept of ECE, SJBIT 1
 Course Learning Objectives

The objectives of the course is to enable students to:

 Impart knowledge of MOS transistor theory and CMOS

technologies
 Learn the operation principles and analysis of inverter
circuits.
 Design Combinational, sequential and dynamic logic
circuits as per the requirements
 Infer the operation of Semiconductors Memory circuits.
 Demonstrate the concepts of CMOS testing
 Module 1:

Introduction: A Brief History, MOS Transistors,

CMOS Logic (1.1 to 1.4 of TEXT2)

MOS Transistor Theory: Introduction, Long-

channel I-V Characteristics, Non-ideal I-V Effects,
DC Transfer Characteristics (2.1, 2.2, 2.4 and 2.5
of TEXT2).
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 Module 2:

Fabrication: CMOS Fabrication and Layout,

VLSI Design Flow, Introduction, CMOS
Technologies, Layout Design Rules, (1.5 and 3.1
to 3.3 of TEXT2).

MOSFET Scaling and Small-Geometry Effects,

MOSFET Capacitances (3.5 to 3.6 of TEXT1)

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 Module 3:

Delay: Introduction, Transient Response, RC

Delay Model, Linear Delay Model, Logical
Efforts of Paths (4.1 to 4.5 of TEXT2, except
sub-sections 4.3.7, 4.4.5, 4.4.6, 4.5.5 and 4.5.6).

Combinational Circuit Design: Introduction,

Circuit families
(9.1 to 9.2 of TEXT2, except subsection 9.2.4).

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 Module 4:
Sequential Circuit Design: Introduction,
Circuit Design for Latches and Flip-Flops (10.1
and 10.3.1 to 10.3.4 of TEXT2)

Dynamic Logic Circuits: Introduction, Basic

Principles of Pass Transistor Circuits,
Synchronous Dynamic Circuit Techniques,
Dynamic CMOS Circuit Techniques (9.1, 9.2,
9.4 to 9.5 of TEXT1)

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 Module 5:

Semiconductor Memories: Introduction,

Dynamic Random Access Memory (DRAM) and
Static Random Access Memory (SRAM),
(10.1 to 10.3 of TEXT1)

Testing and Verification: Introduction, Logic

Verification Principles, Manufacturing Test
Principles, Design for testability
(15.1, 15.3, 15.5 15.6.1 to 15.6.3 of TEXT 2)

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 Course outcomes:

At the end of the course, the students will be able to:

• Demonstrate understanding of MOS transistor theory, CMOS

fabrication flow and technology scaling.
• Draw the basic gates using the stick and layout diagrams with the
knowledge of physical design aspects.
• Demonstrate ability to design Combinational, sequential and
dynamic logic circuits as per the requirements
• Interpret Memory elements along with timing considerations
• Interpret testing and testability issues in VLSI Design
 TEXT BOOKS:

1. “CMOS Digital Integrated Circuits: Analysis and Design”

- Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata
McGraw-Hill.

2. “CMOS VLSI Design- A Circuits and Systems

Perspective”- Neil H. E. Weste, and David Money Harris
4th Edition, Pearson Education.
 REFERENCE BOOKS:

1. Adel Sedra and K. C. Smith, “Microelectronics Circuits

Theory and Applications”, 6th or 7th Edition,
Oxford University Press, International Version, 2009.

2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI

Design”, PHI 3rd Edition, (original Edition –
1994).

3. Behzad Razavi, “Design of Analog CMOS Integrated

Circuits”, TMH, 2007.
 Module 1:

Introduction: A Brief History, MOS Transistors,

CMOS Logic (1.1 to 1.4 of TEXT2)

MOS Transistor Theory: Introduction, Long-

channel I-V Characteristics, Non-ideal I-V Effects,
DC Transfer Characteristics (2.1, 2.2, 2.4 and 2.5
of TEXT2).
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 Introduction

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of
Bell laboratories. In 1961, first IC was introduced.

Levels of Integration:-

i) SSI: - (10-100) transistors => Example: Logic gates

ii) MSI: - (100-1000) => Example: counters

iii) LSI: - (1000-20000) => Example: 8-bit chip

iv) VLSI: - (20000-1000000) => Example: 16 & 32 bit up

v) ULSI: - (1000000-10000000) => Example: Special processors, virtual reality machines,

smart sensors.

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 Moore’s Law:-

•“The number of transistors embedded on the chip doubles after every one and a
half years.” The number of transistors is taken on the y-axis and the years in taken
on the x-axis. The diagram also shows the speed in MHz. the graph given in figure
also shows the variation of speed of the chip in MHz.

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 Classification of Transistors

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 BJT v/s FET

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 A Brief History

• In 1958, Jack Kilby built the first integrated circuit flip-flop

with two transistors at Texas Instruments.
• In 2008, Intel’s Itanium microprocessor contained more than
2 billion transistors and a 16 Gb Flash memory contained
more than 4 billion transistors.
• This corresponds to a compound annual growth rate of 53%
over 50 years.
• This incredible growth has come from steady
miniaturization of transistors and improvements in
manufacturing processes.
• However, as transistors become smaller, they also become
faster, dissipate less power, and are cheaper to manufacture.
 A Brief History

• New fortunes lie ahead for those with innovative

ideas and with talent.
• Ten years later, Jack Kilby at Texas Instruments
realized the potential for miniaturization if multiple
transistors could be built on one piece of silicon.
• The invention of the transistor earned the Nobel
Prize in Physics in 1956 for Bardeen, Brattain, and
their supervisor William Shockley.
• Kilby received the Nobel Prize in Physics in 2000
for the invention of the integrated circuit.
 A Brief History

• Transistors are electrically controlled

switches.
• Bell Labs developed BJT which was more
reliable, less noisy, and more power-
efficient.
• Early integrated circuits primarily used BJT
because they require small current in base
terminal to switch much larger currents
between the emitter and collector.
 A Brief History

• By the 1960s, Metal Oxide Semiconductor Field

Effect Transistors (MOSFETs) began to enter
production.
• MOSFETs draw zero current while idle.
• They are of two types: nMOS and pMOS, using
n-type and p-type silicon.
In 1963, Frank Wanlass at Fairchild described the first logic
gates using MOSFETs and used both nMOS and pMOS
transistors, earning the name Complementary Metal Oxide
Semiconductor, or CMOS.

The circuits used discrete transistors but consumed only

nanowatts of power, six orders of magnitude less than their
bipolar counterparts. With the development of the silicon
planar process, MOS integrated circuits became attractive
for their low cost because each transistor occupied less area
and the fabrication process was simpler.
 Basic MOS Transistors:
MOS:

We should first understand the fact that why the name Metal Oxide Semiconductor
transistor, because the structure consists of a layer of Metal (gate), a layer of oxide (Sio2)
and a layer of semiconductor. Figure 3 below clearly tell why the name MOS.

cross section of a MOS structure

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 We have two types of FETs. They are Enhancement mode and
depletion mode transistor. Also we have PMOS and NMOS
transistors.

• In Enhancement mode transistor channel is going to form after

giving a proper positive gate voltage. We have NMOS and PMOS
enhancement transistors.

• In Depletion mode transistor channel will be present by the

implant. It can be removed by giving a proper negative gate voltage.
We have NMOS and PMOS depletion mode transistors.
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 Metal Oxide Semiconductor(MOS)

Advantages of FET over conventional Transistors

• Unipolar device i. e. operation depends on only one type of charge
carriers (h or e)
• Voltage controlled Device (gate voltage controls drain current)
• Very high input impedance (109-1012 )
• Source and drain are interchangeable in most Low-frequency
applications
• Low Voltage Low Current Operation is possible (Low-power
consumption)
• Less Noisy as Compared to BJT
• No minority carrier storage (Turn off is faster)
• Very small in size, occupies very small space in ICs
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 Transistors as Switches
• We can view MOS transistors as electrically controlled
switches
• Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

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 CMOS Inverter

A Y
0
VDD
1

A Y
A Y

GND

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 CMOS Inverter

A Y
0
VDD
1 0
OFF
A=1 Y=0

ON
A Y
GND

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6/7/2021 Chetana R, Associate Professor, Dept of ECE, SJBIT 28
The NAND
Gate
The NOR
Gate
 Compound
Gates
 A compound gate performing a more complex logic
function in a single stage formed by combination of
series and parallel switch structures.
 For example, the derivation of the circuit for the
function
 Pass Transistors and Transmission
Gates
• An nMOS transistor passes a strong 0. However, the nMOS transistor
is imperfect at passing a 1.
• The high voltage level is somewhat less than VDD, and passes a
degraded or weak 1.
• A pMOS transistor has opposite behavior, passing strong 1s but
degraded 0s.
• The transistor symbols and behaviors are summarized in Figure below
with g, s, and d indicating gate, source, and drain.
• When an nMOS or pMOS is used alone as an imperfect
switch, we sometimes call it a pass transistor.
• By combining an nMOS and a pMOS transistor in parallel
we obtain a switch that turns on when a 1 is applied to g in
which 0s and 1s are both passed in an acceptable fashion.
• We term this a transmission gate or pass gate.
 Tristates

• Figure shows symbols for a tristate buffer. When the

enable input EN is 1, the output Y equals the input A,
just as in an ordinary buffer.
• When the enable is 0, Y is left floating (a ‘Z’ value).
• Sometimes both true and complementary enable
signals EN and EN are drawn explicitly, while
sometimes only EN is shown.
 Multiplexer
s
• Multiplexers are key components in CMOS memory elements and
data manipulation structures.
• A multiplexer chooses the output from among several inputs based
on a select signal.
• A 2-input, or 2:1 multiplexer, chooses input D0 when the select is 0
and input D1 when the select is 1.
• The truth table is given in Table, the logic function is
 Multiplexer
s
• Two transmission gates can be
tied together to form a
compact 2-input multiplexer,
as shown in Figure.
• The select and its
complement enable exactly
one of the two transmission
gates at any given time. The
complementary select S is
often not drawn in the symbol,
as shown in Figure
MOS Transistor Theory: Introduction, Long-channel I-
V Characteristics, Non-ideal I-V Effects, DC Transfer
Characteristics

(2.1, 2.2, 2.4 and 2.5 of TEXT2).

Figure shows some of the symbols that are
commonly used for MOS transistors.
In an nMOS transistor, the majority carriers are electrons in pMOS transistor, the majority
carriers are holes.

Figure shows a simple MOS structure. The top layer of the structure is a good conductor
called the gate.

Transistor gates are now made of polysilicon, i.e., silicon formed from many small crystals.
The middle layer is a very thin insulating film of SiO 2 called the gate oxide.
The bottom layer is the doped body can be n type or p type. The figure shows a p-type body
in which the carriers are holes. The body is grounded and a voltage is applied to the gate. The
gate oxide is a good insulator so almost zero current flows from the gate to the body.
In Figure below , a negative voltage is applied to the
gate, so there is negative charge on the gate.
The mobile positively charged holes are attracted to the
region beneath the gate. This is called the accumulation
mode.
When a small positive voltage is applied to the
gate, resulting in some positive charge on the
gate. The holes in the body are repelled from the
region directly beneath the gate, resulting in a
depletion region forming below the gate.
When a higher positive potential much greater than threshold voltage
Vt is applied, it attracts more positive charge to the gate.
The holes are repelled further and some free electrons in the body are
attracted to the region beneath the gate.
This conductive layer of electrons in the p-type body is called the
inversion layer.
The Figure shows an nMOS transistor. Here the gate-to-
source voltage Vgs is less than the threshold voltage, so
little or no current flows. We say the transistor is OFF,
and this mode of operation is called cutoff.
If the gate voltage is greater
than the threshold voltage an
inversion region of electrons
(majority carriers) called the
channel connects the source and
drain, creating a conductive path
and turning the transistor ON.

The potential difference

between drain and source is
Vds = Vgs -Vgd .

If Vds = 0 (i.e., Vgs = Vgd), there

is no electric field tending to
push current from drain to
source.
When a small positive
potential Vds is applied
to the drain, current Ids
flows through the
channel from drain to
source. This mode of
operation is termed
linear, resistive, triode,
nonsaturated, or
unsaturated; the current
increases with both the
drain voltage
and gate voltage.
If Vds becomes sufficiently large, the channel is no longer
inverted near the drain and becomes pinched off as shown
in Figure. Above this drain voltage the current
Ids is controlled only by the gate voltage and ceases to be
influenced by the drain. This mode is called saturation.
 Long-Channel I-V
Characteristics
The long-channel model assumes that the current through
an OFF transistor is 0.
When a transistor turns ON (Vgs > Vt), the gate attracts
carriers (electrons) to form a channel.
The electrons drift from source to drain at a rate
proportional to the electric field between these regions.
We know that the charge on each plate of a capacitor is Q
= CV. Thus, the charge in the channel Qchannel is
Qchannel = Cg (Vgc –Vt)
where Cg is the capacitance of the gate to the channel
Vgc - Vt is the amount of voltage attracting charge to the
channel beyond the minimum required to invert from p to
n.
We can model the gate as a parallel plate capacitor with
capacitance proportional to area over thickness.

If the gate has length L and width W and the oxide thickness is
tox, the capacitance is

Where Є 0 is the permittivity of free space, 8.85 × 10–14 F/cm, and the
permittivity of SiO2 is kox = 3.9 times as great. Often, the Є ox/tox term is
called Cox, the capacitance per unit area of the gate oxide.
 Each carrier in the channel is accelerated to an average velocity, v,
proportional to the lateral electric field, i.e., the field between
source and drain. The constant of proportionality µ is called the
mobility

A typical value of µ for electrons in an nMOS transistor with low

electric fields is 500–700 cm2/V· s.
The electric field E is the voltage difference between drain and
source Vds divided by the channel length
The time required for carriers to cross the channel is given
by L/v, where L is the channel length and v is the carrier
velocity.

The current between source and drain is the charge in the

channel divided by the time required to cross
If Vds > Vdsat =VGT, the channel is pinched off. Beyond
this point, the drain voltage has no effect on current.
Substituting Vds = Vdsat in equation, we find an
expression for the saturation current that is
independent of Vds.
I-V characteristics of ideal 4/2 λ (a) nMOS and (b) pMOS transistors
• The I-V characteristics of
Nmos transistor is shown.
• The current is zero for gate
voltages below Vt.
• For higher gate voltages,
current increases linearly
with Vds for small Vds .
• As Vds reaches the saturation
point Vdsat = VGT, current
rolls off and eventually
becomes independent of Vds
when the transistor is
saturated.
• pMOS transistors behave in the same way,
but with the signs of all voltages and
currents reversed.
• The I-V characteristics are in the third
quadrant, as shown in Figure.
• The mobility of holes in silicon is typically
lower than that of electrons. This means
that pMOS transistors provide less current
than nMOS
• µn and µp are used to distinguish mobility of
electrons and of holes.
• The mobility ratio µn /µp is typically 2–3; we
will generally use 2 in future.
• The pMOS transistor has the same geometry
as the nMOS in, but with µp = 40 cm2/V· s
and Vtp = – 0.3 V.
 Nonideal I-V Effects

The figure shows simulated I-V characteristics and ideal characteristics. The saturation
current increases less with increasing Vgs
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 Non-ideal I-V Effects
IV characteristics is effected by many second order
effects
– Velocity Saturation
– Mobility Degradation
– Channel Length Modulation
– Body Effect
– Leakage
– Sub threshold region
– Temperature effects
– Noise Margin
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 Velocity Saturation

• The saturation current increases with increasing VGS.

• Velocity saturation and mobility degradation are two of
the effects that cause the current increase with VGS
• When carrier velocity ceases to increase linearly with field
strength we have velocity saturation
 Mobility Degradation

• µ( mobility) = carrier
velocity/Electric field
• As µ increases, doping concentration and
temperature increases
 Channel Length Modulation

• Change in channel length of the transistor because of

Vds is called Channel Length Modulation
• The effective channel length is Leff = L – L’
• For long length channels, channel variation has less
effects, but for sub micron , it is not so.
• Reduction in channel length increases.

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 Body Effect

• MOS device is on a common substrate, so Vsub should

be equal
• But when devices are arranged in series, then Vsub varies and
when Vgs>Vt, space charge occurs
• But if Vsub increases, the width of depletion also
increases and more carriers are trapped within depletion
• Therefore Vsub should be applied such that it balances
the
structure and as a result Vt increases
• Gate voltage necessary to invert channel
• Increases if source voltage increases because source
is connected to the channel
• Increase in Vt with Vs is called the body effect

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 Leakage

• Conduction even when transistor is in

cut-off
• Substrate to diffusion junctions are
reverse biased
• However reverse biased diodes do
conduct leakage current

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 Leakage

• Conduction even when transistor is in

cut-off
• Substrate to diffusion junctions are
reverse biased
• However reverse biased diodes do
conduct leakage current

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 Sub threshold region

• Ideally at VGS < VT, ID = 0.

• The MOS device is partially
conducting for gate voltages below the
threshold voltage.
• This is termed sub-threshold or weak
inversion conduction.

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 Tunnelin
g
• Ideal MOS device has High input impedence and so no static current
flow through the gate terminal.
• But however Carriers “tunnel” through insulating barriers with
finite probability
• Tunneling current is as significant as junction leakage and sub-threshold
conduction.
• So technique to reduce tunneling current is by use of high-K materials
in the gate oxide layer
• High dielectric constant makes high gate capacitance and reduces the
need to reduce the oxide thickness. Silicon Nitride is a good candidate for
such materials.
• If gate oxide is thin, current flows from gate to source or drain, by
tunneling through gate oxide. Current is proportional to area of gate.

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 Temperature Effects

• Temperature has effects on Mobility.

• Carrier mobility decreases with temperature
• Threshold voltage decreases linearly with increase in
temperature
• Junction leakage also increases with increase in
temperature
• Circuit performance is therefore generally worse at high
temperatures
• Conversely cooling can enable better performance
• Cooling techniques
– Convection
• Natural
• Fans
• Heat sinks
– Active cooling
• Water cooling
• Liquid nitrogen
• 05/15/20
Cost of methods have
Chetanato be justified
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 Impact Ionisation( Hot
electron Effects)
• As length of gate decreases, Electric field
at drain increases
• For sub micron length, E is so much
that electrons are of high energy and is termed
hot
• These electrons attract holes toward drain from
substrate and causes substrate current
• This is impact Ionisation
• As a result, there is degradation in device
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 Drain Punch through

When drain is at high voltage, the

depletion region may extend to source,
thus causing current to flow without gate
voltage

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 Noise Margin

Noise Margin: is the allowable noise

that can be present in input without
affecting the output.
NML (noise margin Low) and NMH (noise margin
High)and are defined as:
– NML = VIL(max)- VOL(max)
– NMH = VOH(min) – VIH(max)
• In order to define the terms VIL, VOL, VOH and VIH
again consider the VTC of Inverter as shown in
Figure next.

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 Noise Margin

• NML and NMH are defined

as,
• NML = VIL(max)- VOL(max)
• NMH = VOH(min) –
VIH(max)
• Consider the VTC of Inverter
as shown in Figure.
• The VOH is the maximum
output voltage at which the
output is "logic high".
• The VOL is the minimum
output voltage at which the
output is "logic low".
• The regions of acceptable
high and low voltages
are defined by VIH and
VIL respectively.

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 Noise Margin

• Figure shows the NMH

and NML levels of two
cascaded inverters. The
noise margin shows the
levels of noise when the
gates are connected
together. For the digital
integrated circuits the
noise margin is larger
than '0' and ideally it is
high
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 DC Transfer Characteristics

• The DC transfer characteristics relate

the output to the input voltage.
• Consider the Table, which outlines
various regions of operation for the n-
and p-transistors.
• Vtn & Vtp is threshold voltage of n-
channel & p- channel.
• Note that Vtp is negative.
• As the source of the nMOS transistor
is grounded, Vgsn = Vin and Vdsn =
Vout.
• As the source of the pMOS transistor
is tied to VDD, Vgsp = Vin – VDD and Vdsp
= Vout – VDD.

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 DC Transfer Characteristics

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 DC Transfer Characteristics

• The objective is to find the variation in output

voltage (Vout) as a function of the input voltage
(Vin).
• Given Vin, we must find Vout subject to the
constraint that Idsn = |Idsp|.
• The two transistors shown in Figure is the plot
of Idsn and Idsp in terms of Vdsn and Vdsp for
various values of Vgsn and Vgsp.
• Figure(b) shows the same plot of Idsn and |Idsp|
now in terms of Vout for various values of Vin.
• The possible operating points of the inverter,
marked with dots, are the values of Vout where
Idsn = |Idsp| for a given value of Vin.

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 DC Transfer Characteristics

• These operating points are

plotted on Vout vs. Vin in Figure to
show the inverter DC transfer
characteristics.
• The supply current IDD = Idsn = |
Idsp| is also plotted against Vin in
next figure showing that both
transistors are momentarily ON
as Vin passes through voltages
between GND and VDD, resulting
in a pulse of current drawn from
the power supply.

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 DC Transfer Characteristics

• The operation of the CMOS inverter

can be divided into five regions as
shown.
• The state of each transistor in each
region is shown in Table.
• In region A, the nMOS transistor is OFF
so the pMOS transistor pulls the output
to VDD.
• In region B, the nMOS transistor starts
to turn ON, pulling the output down.
• In region C, both transistors are in
saturation. Notice that ideal transistors
are only in region C for Vin = VDD/2.
• In region D, the pMOS transistor is
partially ON
• In region E, it is completely OFF,
leaving the nMOS transistor to pull the
output down to GND.
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 DC Transfer Characteristics

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 Beta Ratio Effects

• We have seen that for β p = β n, the

inverter threshold voltage Vinv is VDD/2.
• Inverters with different beta ratios r =
β p / β n are called skewed inverters.
• As the beta ratio is changed, the
switching threshold moves. However,
the output voltage transition remains
sharp.
• Gates are usually skewed by adjusting
the widths of transistors while
maintaining minimum length for
speed.

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 Pass Transistor DC
Characteristics

• nMOS transistors pass ‘0’s well but 1s poorly because of threshold drop.
• Similarly, pMOS transistors pass 1s well but 0s poorly.

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 VTU Question Papers

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March 2022
Feb 2023