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EEE 342 Interfacing With 8086

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5 views33 pages

EEE 342 Interfacing With 8086

Uploaded by

poetanonymous11
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Microprocessor Systems and

Interfacing
EEE 342

Dr. Naeem Shehzad


The 8086
 Fairly old microprocessors, but still considered a
good way to introduce the Intel family
 Both microprocessors use 16-bit registers and 20-
bit address bus (supporting 1 MB memory), but:

- The 8086 (1978): 16-bit external data bus


- The 8088 (1979): 8-bit external data bus
Block Diagram

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Block Diagram

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8088
The 8086
8086
Difference between 8086 and 8088
pins

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Physical Memory Organization
(8088)

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Even and Odd Memories (8086)
 The data lines must match the width of the
memory
 Even and Odd Memory Banks
 Two SRAMs are needed. One stores the even bytes
and connects
 to D0-D7, the other stores the odd bytes and connects
to D8-D15 .

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Physical Memory Organization
(8086)

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Even and Odd Memories

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Addressing in 8086

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Even and Odd Memories

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Interfacing Memory chips using
NAND Gate Decoder (8086)
Integrate 64 K Byte RAM with 8086 microprocessors using

NAND address decoding technique. The starting address is


E0000H.

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Integration of Multiple Memory chips
using NAND Gate Decoder (8086)

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Interfacing Memory chips using
NAND Gate Decoder (8086)
Integrate 16 K Byte RAM with 8086 microprocessors using

NAND address decoding technique. The starting address is


C8000H.

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Remember 8086 (When only two
chips)

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Interfacing Memory chips using
NAND Gate Decoder (8086)
Example
Integrate 1 MB RAM with 8086 microprocessors using

NAND address decoding technique. The starting address is


00000H.

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Interfacing Memory chips using
NAND Gate Decoder (8086)
Example
Integrate 1 MB RAM with 8086 microprocessors using line

decoder technique. The available chips size is 64 KB. The


starting address is 00000H.

It will be very complicated to implement it using Nand Gate


Decoder
Hence, we will use line decoder technique

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Interfacing Memory chips using Line
Decoder (8086)

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High-Low Memory Bank

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Interfacing Memory chips using
Separate Bank Decoder (8086)
Example
Integrate 256 KB RAM with 8086 microprocessors using line

decoder technique. The available chips size is 32 KB. The


starting address is 00000H.

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Separate bank write strobe

This technique requires only one decoder for bank


selection
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Interfacing Memory chips using Line
Decoder (8086)
Example
Integrate 512 KB RAM with 8086 microprocessors using line

decoder technique using separate bank write strobe. The


available chips size is 32 KB. The starting address is 00000H.

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Interfacing Memory chips using Line
Decoder (8086)

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Interfacing Memory chips with 8086

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Interfacing Memory chips using Line
Decoder (8086)
Example
Integrate 16 KB RAM and 64 KB of ROM with 8086

microprocessors using line decoder technique using separate


bank write strobe. The available RAM chips size is 2 KB and
ROM size is 8KB. The starting address of RAM is 00000H and
that of ROM is 10000H.

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High-Low Memory Bank

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Interfacing Memory chips using Line
Decoder (8088)
Example
Integrate 32 KB RAM with 8088 microprocessors using line

decoder technique using separate bank 4KB. The starting


address of RAM is 02000H.

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Interfacing Memory chips using Line
Decoder (8086)
Example
Integrate 64 KB RAM with 8086 microprocessors using line

decoder technique using separate bank 8KB. The starting


address of RAM is 02000H.

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Memory Bank
Memory Type Part number Storage capacity
27C16 2KB
27C64 8KB
EPROMs 27C128 16KB
27C256 32KB
27C512 64KB
61C16 2KB
SRAMs
62C256 32KB
28C16 2KB
EEPROMs 28C32 4KB
28C256 32KB

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