Field Programmable Gate Arrays

GUNJAN SHARMA

1
OUTLINE

• Introduction
• FPGA Architecture
• Xilinx Virtex-E
• Design Flow
• Specifications of Design
• Design Entry
• Design Synthesis
• Mapping the Design
• Placing the Design
• Routing the Design
• Bit-stream Generation
• Assigning pins

• Design reports
Why FPGA?

• Custom ICs sometimes designed to replace the large amount of glue logic:
Pros: a. Reduced system complexity.
b. Improved performance.
Cons: a. Very expensive to develop.
b. Delay introduction of product to market (time to market)
because of increased design time.

• Need to worry about two kinds of costs:

a. Cost of development, sometimes
called non-recurring engineering (NRE)
b. Cost of manufacture

• A tradeoff usually exists between

NRE cost and manufacturing costs
Why FPGA? (Continues…)

• The custom IC approach was only viable for products with very high volumes
(where NRE could be amortized), and which were insensitive vis-à-vis time to
market.

• FPGAs were introduced as an alternative to custom ICs for implementing glue

logic:
• Improved density relative to discrete SSI/MSI components (within around 10x of custom ICs)
• With the aid of computer aided design (CAD) tools circuits could be implemented in a short
amount of time (no physical layout process, no mask making, no IC manufacturing)
• lowers NREs
• shortens TTM

• Because of Moore’s law the density (gates/area) of FPGAs continued to grow

through the 80’s and 90’s to the point where major data processing functions
can be implemented on a single FPGA.
FPGA Markets

• FPGA Manufacturers:
• Xilinx (50%)
• Altera (33%)
• Actel, Atmel, Cypress, Lattice, ..

• Market grown rapidly in 2000s

• Not only competing in their “own field”

• Microprocessors
• Microcontrollers
• DSPs
• ASICs
But first, what is inside an FPGA?

• An FPGA is an array of
programmable logic elements
that can be connected to inputs
or outputs.

6
But first, what is inside an FPGA? (Continues…)

• In modern FPGA, other

elements such as RAM, PLLs,
and even microprocessor have
been built within FPGAs.
A Simple FPGA Logic Block
0 0 0 0 0 0 0 ................. 0 1 1

output

a
b FF
c
d

LUT
clk

Logical Cell
Simple Circuit
 LUT Configuration bits

0 0 0 1 0 0 0 ............ 1 1 1

LUT LUT

a ..... 1 0 0 ..... a
b
c FF . . b FF
d c
d

..... 1 .....
. .

0 1 1 1 1 0 0 ............ 1 0 1

LUT LUT

a a
b FF ..... 0 1 0 .....
b
c FF
c d
d . .
Example: FPGA from Xilinx
• Basic blocks are logical cells.
• A slice comprise of two logic cells.
• A configurable logic block (CLB) may have up to 4 slices:
• CLB of XC4000 series have 1 slice.
• CLB of virtex series have 2 or 4 slices.

• A slice from Xilinx Virtex series FPGA contains:

• Two 4 input Look-Up-Table (LUT)
• Two Flip-flop (Registers)
• Carry and control, including multiplexers.

CIN
Source: xilinx.com
Interconnections

• Five type of interconnection based on length

Single length lines, double length lines, Quad, Octal and long lines.

Source: xilinx.com
Programmable Interconnects

• Connection box
• Connects input/output of logic block to interconnect channels.

• Switch box
• Enables the connection of two interconnect lines.

• Transmission gate (or a pass transistor) is used for each connection.

Programmable Interconnects

Snapshot from FPGA Editor

Programmable Switching Matrix
Methods of Interconnection

Direct Interconnect
General
- Connects Purpose
Interconnection
adjacent
Long line CLBs
Interconnect
through direct
--interconnects
Connects
Time criticalgeneral
signals
interconnections and
-without going
Horizontal,
passes through vertical
one&or
throughlong
Global switch
more switchlinesboxes 
boxes  very fast
-slow
Global long lines for
clocks and resets

Source: xilinx.com
Xilinx : Virtex-E (Floorplan)

Source: xilinx.com
Virtex-E Configurable Logic Block (CLB)

Source: xilinx.com
Details of Virtex-E Slice
COUT

CIN

Source: xilinx.com
Virtex-E Input/Output Block (IOB) Detail

Source: xilinx.com
DESIGN FLOW

Specifications
• Specifications of Design.

• Converting into HDL. HDL Simulation

• To implement a HDL design into an

FPGA several steps are required: Synthesis

• Synthesize Design
• Map design Technology
Mapping
• Placing design inside FPGA
• Routing design inside FPGA
• Convert final design into a bit stream for Place&Route Simulation
programming PFGA

• Those steps are usually performed by Bit-file

automated tools, but it is also possible to do

some part manually
FPGA
Specifications

• To add two 64-bit binary numbers with an additional carry in and

generate a 64-bit output and 1-bit carry out.

cout

64
a
64
64-BIT sum
64 ADDER
b

cin
Specifications
Specifications

HDL
(Behavioral)
Synthesis

Schematic Technology
Technology Mapping
Mapping

Place&Route
Place&Route Simulation

FPGA
Bit-file
Bit-file

FPGA
FPGA
How do we go from
This… To This…

library IEEE;
library
use IEEE;
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
use IEEE.STD_LOGIC_ARITH.ALL;
IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_g is
entity add_g
generic is
(x : natural := 63);
generic (x : natural := 63);
port (a : in std_logic_vector (x downto 0);
b port (a : in std_logic_vector
: in std_logic_vector (x downto
(x downto 0); 0);
b : in std_logic_vector
cin : in std_logic; (x downto 0);
cin :: out
sum in std_logic;
std_logic_vector (x downto 0);
sum
cout : out: out std_logic_vector (x downto 0);
std_logic);
cout : out std_logic);
end entity add_g;
end entity add_g;
architecture behavior of add_g is
architecture
begin -- behavior behavior of add_g is
begin -- behavior
adder: process(a,b,cin)
adder: carry
variable process(a,b,cin)
: std_logic;
variable
variable isum carry : std_logic;
: std_logic_vector(x downto
variable
0); isum : std_logic_vector(x downto
0);
begin
begin
carry := cin;
carry
for i in := cin;
0 to x loop
for i in
isum(i) :=0 toa(i)
x loop
xor b(i) xor carry;
carry := (a(i)a(i)
isum(i) := andxor b(i)orxor
b(i)) carry;
(a(i) and
carry := (a(i) and
carry) or (b(i) and carry);b(i)) or (a(i) and
carry)
end loop; or (b(i) and carry);
end<=
sum loop;
isum;
cout <=<=
sum isum;
carry;
cout <=
end process adder; carry;
end
end process adder;
architecture behavior;
end architecture behavior;
Design Entry

Snapshot from Xilinx ISE

Synthesizing the design

• Synthesis : Optimization process of adapting a logic design to the logic

resources available on the chip, like lookup tables, Long line, and
dedicated carry.

• It means analyzing the whole design, and selecting which logic resources
available in the FPGA will be used to perform the task.

• Gate level netlist is the output file.

Synthesis - Example

library IEEE;
library
use IEEE;
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
use IEEE.STD_LOGIC_ARITH.ALL;
IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_g is
entity add_g
generic is
(x : natural := 63);
generic (x : natural := 63);
port (a : in std_logic_vector (x downto 0);
b port (a : in std_logic_vector
: in std_logic_vector (x downto
(x downto 0); 0);
b : in std_logic_vector
cin : in std_logic; (x downto 0);
cin :: out
in std_logic;
sum
sum : out
std_logic_vector (x downto 0);
std_logic_vector (x downto 0);
After synthesis,
cout : out std_logic);
cout : out std_logic);
end entity add_g;
we get:
end entity add_g;
architecture behavior of add_g is
architecture
begin -- behavior behavior of add_g is
begin -- behavior
adder: process(a,b,cin)
adder: carry
variable process(a,b,cin)
: std_logic;
variable
variable isum carry : std_logic;
: std_logic_vector(x downto
variable
0); isum : std_logic_vector(x downto
0);
begin
begin
carry := cin;
carry
for i in := cin;
0 to x loop
for i in
isum(i) :=0 toa(i)
x loop
xor b(i) xor carry;
carry := (a(i)a(i)
isum(i) := andxor b(i)orxor
b(i)) carry;
(a(i) and
carry := (a(i) and
carry) or (b(i) and carry);b(i)) or (a(i) and
carry)
end loop; or (b(i) and carry);
end<=
sum loop;
isum;
cout <=<=
sum isum;
carry;
cout <=
end process adder; carry;
end
end process adder;
architecture behavior;
end architecture behavior;
Mapping the design

• Mapping : Process of assigning portions of the logic design to the physical

chip resources (CLBs).

• Function similar to synthesizing.

• Synthesizing is not necessarily specific to a particular FPGA, but mapping

usually is.
Mapping the design (Continues…)

Snapshot from FPGA Editor

Placing the design

• Placing : In FPGAs, the process of assigning specific parts of the design to

specific locations (CLBs) on the chip.

• Usually done automatically.

• Once the design has been converted into the logic resources of the FPGA,
we find a location for these within the FPGA.
Placing the design (Continues…)

Snapshot from FPGA Editor

Routing the design

• Routing : The process of creating the desired interconnection of logic cells

to make them perform the desired function.

• Routing follows after placement.

• Once logic resources have been assigned a location within the FPGA, we
need to interconnect the logic resources using internal buses inside the
FPGA.
Routing the design (Continues…)

Snapshot from FPGA Editor

Routing the design (Continues…)

Snapshot from FPGA Editor

Convert design into bit stream

• This always done using an automated tools.

• The placed and routed designed is converted into a bit-stream that is

downloaded into the FPGA to configure it
Convert design into bit stream (Continues…)

Bit-stream Configuration
Assigning pins

• When implementing an entity in FPGA, the input and output ports are
mapped to pins of the FPGA

entity add_g is
entity add_g
generic is
(x : natural := 63);
generic (x : natural := 63); a(63:0) cin
port (a : in std_logic_vector (x downto
0);port (a : in std_logic_vector (x downto b(63:0) FPGA
b 0);
: in std_logic_vector (x downto 0);
b ::in
cin in std_logic_vector
std_logic; (x downto 0); cout
cin : in std_logic;
sum : out std_logic_vector (x downto 0); sum(63:0)
sum
cout : out: out std_logic_vector (x downto 0);
std_logic);
cout : out
end entity add_g; std_logic);
end entity add_g;
Assigning pins (Continues…)

• A file called a UCF (User Constraint File) is used to define which pin will be
connected to a particular input or output.

• Example of UCF file:

entity add_g is
entity add_g
generic is
(x : natural := 63);
generic (x : natural := 63);
NET "cin" LOC = "T9";
port (a : in std_logic_vector (x NET
NET "cin"
“cout" LOC
LOC == "T9";;
"M13"
port (a0);
downto : in std_logic_vector (x NET “cout" LOC = "M13" ;
b downto 0);
: in std_logic_vector (x
b : in std_logic_vector
downto 0); (x
downto
cin 0);
: in std_logic;
cin :: out
sum in std_logic;
std_logic_vector (x
sum : 0);
downto out std_logic_vector (x
downto
cout : out 0);
std_logic);
cout
end : outadd_g;
entity std_logic);
end entity add_g;

• Within Xilinx Project manager, the “assign package pin” function can be
used to easily define input and output pin location.
Design Summary

Snapshot from Xilinx ISE

Synthesis Report

Snapshot from Xilinx ISE

Synthesis Report – Device Utilization Summary

Snapshot from Xilinx ISE

Synthesis Report – Timing Report

Snapshot from Xilinx ISE

Thank You