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L3 - Representing Instructions in The Computer

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35 views13 pages

L3 - Representing Instructions in The Computer

Uploaded by

Hari Kalyan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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REPRESENTING

INSTRUCTIONS IN THE
COMPUTER
REPRESENTING INSTRUCTIONS IN THE
COMPUTER
 Instructions are kept in the computer as a series of high
and low electronic signals
 Represented as numbers

 Each piece of an instruction can be considered as an


individual number
 Placing these numbers side by side forms the instruction

 Translating ARM Assembly Instructions into a Machine


Instructions
 Real ARM language version of the instruction represented
symbolically as
 ADD r5, r1, r2

 First as a combination of decimal numbers and then of


binary numbers
ARM FIELDS
Cond F I Opcode S Rn Rd Operand2

4 bits 2 bits 1 bit 4 bits 1 bit 4 bits 4 bits 12 bits

 Opcode - Basic operation of the instruction


 Rd -The register destination operand. It gets the result of the
operation
 Rn - The first register source operand
 Operand2 - The second source operand
 I - Immediate
If I = 0 second source operand is register
If I = 1 second source operand is 12 bit immediate
(constant)
 S - Set condition code. Related to conditional branch
instruction
 Cond - Condition. Related to conditional branch instruction
 F - Instruction format. Allows ARM to different instruction
format when needed
ARM INSTRUCTION ENCODING
Instruction Format Cond F I Op S Rn Rd Operand

ADD DP 14 0 0 4 0 Reg Reg Reg


SUB DP 14 0 0 2 0 Reg Reg Reg
ADD DP 14 0 1 4 0 Reg Reg constant
(immediate
)
LDR (load DT 14 1 n.a. 24 n.a. Reg Reg Address
word)
STR (store DT 14 1 n.a. 25 n.a. Reg Reg Address
word)

 Reg - Register number between 0 and 15


 Constant => 12 bit constant

 Address => 12 bit address

 Op => Opcode
DECIMAL REPRESENTATION OF INSTRUCTION
 ADD r5, r1, r2
14 0 0 4 0 1 5 2

 Each of these segments of an instruction is called a field


 Fourth field containing 4 - Tells the ARM computer that this
instruction performs addition
 The sixth field - Gives the number of the register that is the
first source operand of the addition operation (1 = r1)
 The last field - Gives the other source operand for the
addition (2 = r2)
 The seventh field contains - The number of the register that is
to receive the sum
 This instruction adds register r1 to register r2 and places the
sum in the register r5
INSTRUCTION FORMAT
 Layout of instruction
 Instruction represented as fields of binary numbers

 32 bit long

1110 00 0 0100 0 0001 0101 000000000010


4 bits 2 bits 1 bit 4 bits 1 bit 4 bits 4 bits 12 bits
 Numeric version of instructions machine language
and a sequence of such instructions machine code
 Instruction format - A form of representation of an
instruction composed of fields of binary numbers
 Machine language - Binary representation used for
communication within a computer system
ARM INSTRUCTION FORMAT
Cond F Opcode Rn Rd Offset12

4 bits 2 bits 6 bits 4 bits 4 bits 12 bits

 Data processing (DP) instruction format


 Data transfer (DT) instruction format

 Although multiple formats complicate the hardware


Complexity is reduced by keeping the formats similar
 For example, the first two fields and last three fields of the
two formats are the same size and four of them have the
same names
 The length of the opcode field in DT format is equal to the
sum of the lengths of three fields of DP format
ARM FIELDS (2)
 ADD r3, r3, #4 ; r3=r3+4
 Constant 4 is placed in operand 2 field and the I field is set to 1
14 0 1 4 0 3 3 4

 LDR r5, [r3, #32] ; Temporary register r5 gets A[8]


 Load and store use a different instruction format from above with
6 fields

 Field F = 1 => Tell ARM that format is different


 Data transfer instruction format
 Opcode field 24 => instruction perform load word
 Offset12 field has 32 as the offset to add to the base register
TRANSLATING ARM ASSEMBLY
LANGUAGE INTO MACHINE LANGUAGE
 Consider an example all the way from what the programmer
writes to what the computer executes
 If r3 has the base of the array A and r2 corresponds to h, the
assignment statement
 A[30] = h + A[30]; is compiled into

 LDR r5, [r3, #120] # Temporary reg r5 gets A[30]


 ADD r5, r2, r5 # Temporary reg r5 gets h + A[30]
 STR r5, [r3, #120] # Stores h + A[30] back into A[30]

 What is the ARM machine language code for these three


instructions?
MACHINE LANGUAGE INSTRUCTION
USING DECIMAL NUMBERS

Cond F I Opcode S Rn Rd Operand2


/Offset12
14 1 24 3 5 120
14 0 0 4 0 2 5 5
14 1 25 3 5 120
MACHINE LANGUAGE INSTRUCTION
USING BINARY NUMBERS
Cond F I Opcode S Rn Rd Operand2/
Offset12

1110 1 11000 0011 0101 0000


0111
1 000

1110 0 0 100 0 0010 0101 0000


0000
0101
1110 1 11001 0011 0101 0000
0111
1 000
ARM MACHINE LANGUAGE
Name Format Example Comments

ADD DP 14 0 0 4 0 2 1 3 ADD
r1,r2,r3
SUB DP 14 0 0 2 0 2 1 3 SUB
r1,r2,r3
LDR DT 14 1 24 2 1 100 LDR r1,
100(r2)
STR DT 14 1 25 2 1 100 STR r1,
100(r2)
Field 4 bits 2 1 bit 4 bits 1 4 4 12 bits All ARM
size bits bit bits bits instructions
are 32 bits
long
DP DP Cond F I Opcode S Rn Rd Operan Arithmetic
format d2 instruction
format

DT DT Cond F Opcode Rn Rd Offset1 Data


format 2 transfer
format
What ARM instruction does this represent?

Cond F I Opcode S Rn Rd Operand2

14 0 0 4 0 0 1 2

 ADD r0, r1, r2


 ADD r1, r0, r2

 ADD r2, r1, r0

 SUB r2, r0, r1

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