Synchronous Sequential Logic

Chapter 5
 5-1 Introduction
 Combinational circuits
 contains no memory elements
 the outputs depends on the inputs

Digital Circuits 5-2

 5-2 Sequential Circuits
■ Sequential circuits

 a feedback path
 the state of the sequential circuit
 (inputs, current state) Þ (outputs, next state)
 synchronous: the transition happens at discrete
instants of time
 asynchronous: at any instant of time

Digital Circuits 5-3

 Synchronous sequential circuits
 a master-clock generator to generate a periodic
train of clock pulses
 the clock pulses are distributed throughout the
system
 clocked sequential circuits
 most commonly used
 no instability problems
 the memory elements: flip-flops
 binary cells capable of storing one bit of information
 two outputs: one for the normal value and one for the
complement value
 maintain a binary state indefinitely until directed by an
input signal to switch states

Digital Circuits 5-4

Fig. 5.2
Synchronous clocked sequential circuit
Digital Circuits 5-5
5-3 Latches
 Basic flip-flop circuit
 two NOR gates

 more complicated types can be built upon it

 directed-coupled RS flip-flop: the cross-coupled connection
 an asynchronous sequential circuit
 (S,R)= (0,0): no operation
(S,R)=(0,1): reset (Q=0, the clear state)
(S,R)=(1,0): set (Q=1, the set state)
(S,R)=(1,1): indeterminate state (Q=Q'=0)
 consider (S,R) = (1,1) Þ (0,0) Digital Circuits 5-6
  SR latch with NAND gates

Fig. 5.4
SR latch with NAND gates

Digital Circuits 5-7

  SR latch with control input
 En=0, no change
 En=1, output depends inputs S, R

S_ 1/S'

0/1

R_ 1/R'

Fig. 5.5
SR latch with control input
Digital Circuits 5-8
  D Latch
 eliminate the undesirable conditions of the
indeterminate state in the RS flip-flop
 D: data
 gated D-latch
 D Þ Q when En=1; no change when En=0
S_ 1/D'

0/1

R_ 1/D

Fig. 5.6
D latch
Digital Circuits 5-9
Fig. 5.7
Graphic symbols for latches

Digital Circuits 5-10

 5-4 Flip-Flops
 A trigger
 The state of a latch or flip-flop is switched by a
change of the control input
 Level triggered – latches
 Edge triggered – flip-flops

Fig. 5.8
Clock response in latch and flip-flop
Digital Circuits 5-11
 If level-triggered flip-flops are used
 the feedback path may cause instability problem
 Edge-triggered flip-flops
 the state transition happens only at the edge
 eliminate the multiple-transition problem

Digital Circuits 5-12

 Edge-triggered D flip-flop
 Master-slave D flip-flop
 two separate flip-flops
 a master flip-flop (positive-level triggered)
 a slave flip-flop (negative-level triggered)

Fig. 5.9
Master-slave D flip-flop
Digital Circuits 5-13
 CP = 1: (S,R) Þ (Y,Y'); (Q,Q') holds
 CP = 0: (Y,Y') holds; (Y,Y') Þ (Q,Q')
 (S,R) could not affect (Q,Q') directly
 the state changes coincide with the negative-edge
transition of CP

Digital Circuits 5-14

  Edge-triggered flip-flops
 the state changes during a clock-pulse transition
 A D-type positive-edge-triggered flip-flop

Fig. 5.10
D-type positive-edge-
triggered flip-flop Digital Circuits 5-15
 three basic flip-flops
 (S,R) = (0,1): Q = 1
 (S,R) = (1,0): Q = 0
 (S,R) = (1,1): no operation
 (S,R) = (0,0): should be avoided

Fig. 5.10
D-type positive-edge-
triggered flip-flop
Digital Circuits 5-16
Digital Circuits 5-17
  The setup time
 D input must be maintained at a constant value prior to the
application of the positive CP pulse
 The hold time
 D input must not changes after the application of the positive
CP pulse

 The propagation delay time

 The interval between the trigger edge and the stabilization
of the output to a new state
50% VH 50% VH

50% VH 50% VH

Digital Circuits 5-18

 Summary
 CP=0: (S,R) = (1,1), no state change
 CP=: state change once
 CP=1: state holds

Digital Circuits 5-19

 Other Flip-Flops
 The edge-triggered D flip-flops
 The most economical and efficient
 Positive-edge and negative-edge

Fig. 5.11
Graphic symbols for edge-
triggered D flip-flop Digital Circuits 5-20
 JK flip-flop

 D=JQ'+K'Q Fig. 5.12

 J=0, K=0: D=Q, no change JK flip-flop
 J=0, K=1: D=0 Þ Q =0
 J=1, K=0: D=1 Þ Q =1
 J=1, K=1: D=Q' Þ Q =Q'
Digital Circuits 5-21
  T flip-flop

Fig. 5.13
T flip-flop

 D = T⊕Q = TQ'+T'Q
 T=0: D=Q, no change
 T=1: D=Q' Þ Q=Q'

Digital Circuits 5-22

 Characteristic tables

Digital Circuits 5-23

 Characteristic equations
 D flip-flop
 Q(t+1) = D
 JK flip-flop
 Q(t+1) = JQ'+K'Q
 T flop-flop
 Q(t+1) = T⊕Q

Digital Circuits 5-24

Direct inputs
 asynchronous set and/or asynchronous reset

Fig. 5.14
D flip-flop with asynchronous reset
Digital Circuits 5-25
 5-5 Analysis of Clocked Sequential Ckts
 A sequential circuit
 (inputs, current state) Þ (output, next state)
 a state transition table or state transition diagram

Fig. 5.15
Example of sequential circuit
Digital Circuits 5-26
State equations
 A(t+1) = A(t)x(t) + B(t)x(t)
 B(t+1) = A'(t)x(t)
 A compact form
 A(t+1) = Ax + Bx
 B(t+1) = Ax
 The output equation
 y(t) = (A(t)+B(t))x'(t)
 y = (A+B)x'

Digital Circuits 5-27

State table
 State transition table
 = state equations

Digital Circuits 5-28

State equation

A(t + 1) =Ax + Bx
B(t + 1) = Ax
y = Ax + Bx

Digital Circuits 5-29

 State diagram
 State transition diagram
 a circle: a state
 a directed lines connecting the circles: the
transition between the states
 Each directed line is labeled 'inputs/outputs‘

Fig. 5.16
State diagram of the circuit
of Fig. 5.15

 a logic diagram Û a state table Û a state diagram

Digital Circuits 5-30
Flip-flop input equations
 The part of circuit that generates the inputs to
flip-flops
 Also called excitation functions
 DA = Ax +Bx
 DB = A'x
 The output equations
 to fully describe the sequential circuit
 y = (A+B)x'

Digital Circuits 5-31

Analysis with D flip-flops
 The input equation
 DA=A⊕x⊕y
 The state equation
 A(t+1)=A⊕x⊕y

Fig. 5.17
Sequential circuit with D flip-flop
Digital Circuits 5-32
Analysis with JK flip-flops
 Determine the flip-flop input function in terms of
the present state and input variables
 Used the corresponding flip-flop characteristic
table to determine the next state

Fig. 5.18
Sequential circuit with JK
flip-flop
Digital Circuits 5-33
 JA = B, KA= Bx'
 JB = x', KB = A'x + Ax‘
 derive the state table

 Or, derive the state equations using characteristic eq.

Digital Circuits 5-34
  State transition diagram

A(t  1)  JA  K A
B (t  1)  JB  K B

State equation for A and B:

A(t  1)  BA  ( Bx) A  AB  AB  Ax

B (t  1)  x B  ( A  x )B  Bx  ABx  ABx 

Fig. 5.19
State diagram of the circuit of Fig. 5.18

Digital Circuits 5-35

Analysis with T flip-flops
 The characteristic equation
 Q(t+1)= T⊕Q = TQ'+T'Q
Fig. 5.20
Sequential circuit with T
flip-flop

Digital Circuits 5-36

 The input and output functions
 TA=Bx
 TB= x
 y = AB
 The state equations
 A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx
 B(t+1) = x⊕B

Digital Circuits 5-37

State Table

Digital Circuits 5-38

Mealy and Moore models
 the Mealy model: the outputs are functions of
both the present state and inputs (Fig. 5-15)
 the outputs may change if the inputs change
during the clock pulse period
 the outputs may have momentary false values unless the
inputs are synchronized with the clocks
 The Moore model: the outputs are functions
of the present state only (Fig. 5-20)
 The outputs are synchronous with the clocks

Digital Circuits 5-39

Fig. 5.21
Block diagram of Mealy and Moore state machine
Digital Circuits 5-40
 5-7 Synthesizable HDL Models of Sequential
Circuits
 Behavioral Modeling
Example: Two ways to provide free-running clock

Example: Another way to describe free-running clock

Digital Circuits 5-41

 Behavioral Modeling
 always statement

Examples:

Two procedural blocking assignments: Two nonblocking assignments:

Digital Circuits 5-42

Characteristic Equation
Q(t + 1) = Q ⊕ T For a T flip-flop
Q(t + 1) = JQ + KQ For a JK flip-flop
■ HDL Example 5.3

Digital Circuits 5-43

 5-7 State Reduction and Assignment
 State Reduction
 reductions on the number of flip-flops and the
number of gates
 a reduction in the number of states may result in a
reduction in the number of flip-flops
 a example state diagram

Fig. 5.25 State diagram

Digital Circuits 5-44
 state a a b c d e f f g f g a
input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0
 only the input-output sequences are important
 two circuits are equivalent
 have identical outputs for all input sequences
 the number of states is not important

Fig. 5.25 State diagram

Digital Circuits 5-45
 Equivalent states
 two states are said to be equivalent
 for each member of the set of inputs, they give exactly
the same output and send the circuit to the same state or
to an equivalent state
 one of them can be removed

Digital Circuits 5-46

 Reducing the state table
 e=f
 d=?

Digital Circuits 5-47

 the reduced finite state machine

 state a a b c d e d d e d e a
input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0
Digital Circuits 5-48
 the checking of each pair of states for possible
equivalence can be done systematically (9-5)
 the unused states are treated as don't-care
condition Þ fewer combinational gates

Fig. 5.26
Reduced State diagram
Digital Circuits 5-49
State assignment
 to minimize the cost of the combinational circuits
 three possible binary state assignments

Digital Circuits 5-50

 any binary number assignment is satisfactory as
long as each state is assigned a unique number
 use binary assignment 1

Digital Circuits 5-51

5-8 Design Procedure
 the word description of the circuit behavior (a state
diagram)
 state reduction if necessary
 assign binary values to the states
 obtain the binary-coded state table
 choose the type of flip-flops
 derive the simplified flip-flop input equations and
output equations
 draw the logic diagram

Digital Circuits 5-52

 Synthesis using D flip-flops
 An example state diagram and state table

Fig. 5.27
State diagram for
sequence detector
Digital Circuits 5-53
 The flip-flop input equations
 A(t+1) = DA(A,B,x) = S(3,5,7)
 B(t+1) = DB(A,B,x) = S(1,5,7)
 The output equation
 y(A,B,x) = S(6,7)
 Logic minimization using the K map
 DA= Ax + Bx
 DB= Ax + B'x
 y = AB

Digital Circuits 5-54

Fig. 5.28
Maps for sequence detector

Digital Circuits 5-55

 Sequence detector
 The logic diagram

Fig. 5.29
Logic diagram of
sequence detector
Digital Circuits 5-56
Excitation tables
 A state diagram Þ flip-flop input functions
 straightforward for D flip-flops
 we need excitation tables for JK and T flip-flops

Digital Circuits 5-57

Synthesis using JK flip-flops
 The same example
 The state table and JK flip-flop inputs

Digital Circuits 5-58

  JA = Bx'; KA = Bx
 JB = x; KB = (A⊕x)‘
 y=?

Fig. 5.30
Maps for J and K
input equations Digital Circuits 5-59
Fig. 5.31
Logic diagram for sequential
circuit with JK flip-flops
Digital Circuits 5-60
 Synthesis using T flip-flops
 A n-bit binary counter
 the state diagram

Fig. 5.32
State diagram of three-
bit binary counter
 no inputs (except for the clock input)

Digital Circuits 5-61

 The state table and the flip-flop inputs

Digital Circuits 5-62

Fig. 5.33
Maps of three-bit binary
counter

Digital Circuits 5-63

  Logic simplification using the K map
 TA2 = A1A2
 TA1 = A0
 TA0 = 1
 The logic diagram

Fig. 5.34
Logic diagram of three-bit
binary counter
Digital Circuits 5-64