Gate-Level Minimization

Chapter 3
3-1 Introduction
• Gate-level minimization refers to the design task of finding an optimal
gate-level implementation of Boolean functions describing a digital
circuit.

3-2
3-2 The Map Method
• The complexity of the digital logic gates
• the complexity of the algebraic expression
• Logic minimization
• algebraic approaches: lack specific rules
• the Karnaugh map
• a simple straight forward procedure
• a pictorial form of a truth table
• applicable if the # of variables < 5
• If there are more than 5 variables, it is still possible to use Karnaugh maps, and you will find larger
Karnaugh maps discussed in many textbooks. However, as the number of variables increases it
becomes more difficult to see patterns, and computer methods start to become more attractive.
• A diagram made up of squares
• each square represents one minterm

3-3
• Boolean function
• sum of minterms
• sum of products (or product of sum) in the simplest form
• a minimum number of terms
• a minimum number of literals
• The simplified expression may not be unique

3-4
Two-Variable Map
• A two-variable map
• four minterms
• x' = row 0; x = row 1
• y' = column 0;
y = column 1
• a truth table in square
diagram
• xy
• x+y =

Fig. 3.2 Representation of functions

in the map 3-5
A three-variable map
• eight minterms
• the Gray code sequence
• any two adjacent squares in the map differ by only on
variable
• primed in one square and unprimed in the other
• e.g., m5 and m7 can be simplified
• m5+ m7 = xy'z + xyz = xz (y'+y) = xz

3-6
• Example 3-1
• F(x,y,z) = S(2,3,4,5)
• F = x'y + xy'

3-7
• m0 and m2 (m4 and m6) are adjacent
• m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
• m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

3-8
• Example 3-2
• F(x,y,z) = S(3,4,6,7) = yz+ xz'

3-9
• Four adjacent squares
• 2, 4, 8 and 16 squares
• m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz'
= x'z'(y'+y)
+xz'(y'+y) =
x'z' + xz‘ = z'
• m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz
=x'z(y'+y) + xz(y'+y)
=x'z + xz =
z

3-10
• Example 3-3
• F(x,y,z) = S(0,2,4,5,6)
• F = z'+ xy'

3-11
• Example 3-4
• F = A'C + A'B + AB'C + BC
• express it in sum of minterms
• find the minimal sum of products expression

3-12
3-3 Four-Variable Map
• The map
• 16 minterms
• combinations of 2, 4, 8, and 16 adjacent squares

3-13
 • Example 3-5
• F(w,x,y,z) = S(0,1,2,4,5,6,8,9,12,13,14)

 F = y'+w'z'+xz'

3-14
• Example 3-6 Simplify the Boolean function

F = ABC + BCD + ABCD + ABC

3-15
• Prime Implicants
• all the minterms are covered
• minimize the number of terms
• a prime implicant: a product term obtained by combining the maximum
possible number of adjacent squares (combining all possible maximum
numbers of squares)
• essential: a minterm is covered by only one prime implicant, that prime
implicant is called essential

3-16
 Consider F ( A, B, C , D )   (0, 2,3,5,7,8,9,10,11,13,15)
• the simplified expression may not be unique
• F = BD+B'D'+CD+AD = BD+B'D'+CD+AB
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'

3-17
3-4 Five-Variable Map
• Map for more than four variables becomes
complicated
• five-variable map: two four-variable map (one on the
top of the other)

3-18
• Example 3-7
• F = S(0,2,4,6,9,13,21,23,25,29,31)

F = A'B'E'+BD'E+ACE 3-19
3-5 Product of Sums Simplification
• Approach #1
• Simplified F' in the form of sum of products
• Apply DeMorgan's theorem F = (F')'
• F': sum of products => F: product of sums
• Approach #2: duality
• combinations of maxterms (like it was minterms)
• M0M1 = (A+B+C+D)(A+B+C+D') = (A+B+C)+(DD')
= A+B+C
CD
AB 00 01 11 10
00 M0 M1 M3 M2
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10
3-20
• Example 3-8
• F = S(0,1,2,5,8,9,10)

• F' = AB+CD+BD'
• Apply DeMorgan's theorem; F=(A'+B')(C'+D')(B'+D)
• Or think in terms of maxterms
3-21
• Gate implementation of the function of Example 3-8

3-22
• Consider the function defined in
Table 3.2.

In sum-of-minterm:
F ( x, y , z )   (1,3, 4,6)

In product-of-maxterm:

F ( x, y, z )   (0, 2, 5, 7)

3-23
• Consider the function defined in
Table 3.2.
F ( x, y , z )  x z  xz 

Combine the 1’s:

F  xz  xz 
Combine the 0’s :

F   xz  xz 
Taking the complement of F
F ( x, y , z )  ( x  z)( x  z )
3-24
3-6 Don't-Care Conditions
• The value of a function is not specified for certain combinations of
variables
• BCD; 1010-1111: don't care
• The don't care conditions can be utilized in logic minimization
• can be implemented as 0 or 1
• Example 3-9
• F (w,x,y,z) = S(1,3,7,11,15)
• d(w,x,y,z) = S(0,2,5)

3-25
 • F = yz + w'x'; F = yz + w'z
• F = S(0,1,2,3,7,11,15) ; F = S(1,3,5,7,11,15)
• either expression is acceptable

• Also apply to products of sum

3-26
3-7 NAND and NOR Implementation
• NAND gate is a universal gate
• can implement any digital system

3-27
• Two graphic symbols for a NAND gate

3-28
Two-level Implementation
• two-level logic
• NAND-NAND = sum of products
• Example: F = AB+CD
• F = ((AB)' (CD)' )' =AB+CD

Fig. 3-20
Three ways to implement
F = AB + CD

3-29
• Example 3-10

F ( x, y , z )   (1, 2,3, 4,5,7) F ( x, y , z )  xy   xy  z

3-30
• The procedure
• simplified in the form of sum of products
• a NAND gate for each product term; the inputs to each NAND gate are the
literals of the term
• a single NAND gate for the second sum term

3-31
Multilevel NAND Circuits
• Boolean function implementation
• AND-OR logic => NAND-NAND logic
• AND => NAND + inverter
• OR: inverter + OR = NAND

Fig. 3.22
Implementing F = A(CD + B) + BC 3-32
NAND Implementation

Fig. 3.23
Implementing
F = (AB +AB)(C+ D)
3-33
NOR Implementation
• NOR function is the dual of NAND function
• The NOR gate is also universal

3-34
 • Two graphic symbols for a NOR gate

Example: F = (A + B)(C + D)E

Fig. 3.26
Implementing
F = (A + B)(C + D)E 3-35
Example: F = (AB +AB)(C + D)

Fig. 3.27
Implementing F = (AB +AB)(C + D) with NOR gates
3-36
• Boolean-function implementation
• OR => NOR + INV
• AND
• INV + AND = NOR

3-37
3-38
3-39
3-9 Exclusive-OR Function
• Exclusive-OR (XOR)
• xÅy = xy'+x'y
• Exclusive-NOR (XNOR)
• (xÅy)' = xy + x'y'
• Some identities
• xÅ0 = x
• xÅ1 = x'
• xÅx = 0
• xÅx' = 1
• xÅy' = (xÅy)'
• x'Åy = (xÅy)'
• Commutative and associative
• AÅB = BÅA
• (AÅB) ÅC = AÅ (BÅC) = AÅBÅC
3-40
• Implementations
• (x'+y')x + (x'+y')y = xy'+x'y = xÅy

3-41
Odd function
• AÅBÅC = (AB'+A'B)C' +(AB+A'B')C =
AB'C'+A'BC'+ABC+A'B'C = S(1,2,4,7)
• an odd number of 1's

3-42
• Logic diagram of odd and even functions

3-43
• Four-variable Exclusive-OR function
• AÅBÅCÅD = (AB’+A’B)Å(CD’+C’D) =
(AB’+A’B)(CD+C’D’)+(AB+A’B’)(CD’+C’D)

3-44
Parity Generation and Checking
• Parity Generation and Checking
• a parity bit: P = xÅyÅz
• parity check: C = xÅyÅzÅP
• C=1: an odd number of data bit error
• C=0: correct or an ever # of data bit error

3-45
Parity Generation and Checking

3-46
Parity Generation and Checking

3-47