UART INTERFACE WITH FPGA

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What you will Learn Today
 Introduction to UART
 VHDL CODE –UART Transmitter
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Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3
DSP Architecture: Blackfin,C2000,C6000,21065L Sharc
FPGA: Spartan,Virtex,Cyclone
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● Only Xilinx FPGA and tools will be covered.
Spartan 6 FPGA Board

● Xilinx’s Spartan®-6
XC6SLX16-2FTG256C
● MT41J128M16JT-25(DDR3)
● 50MHz Clock
● M25P80 SPI Flash
Board Specifications
● On-Board FPGA: XC6SLX16-2FTG256C;
● On-Board FPGA external crystal frequency: 50MHz;
● XC6SLX16-2FTG256C has rich block RAM resource up to 576Kb
● XC6SLX16-2FTG256C has 14,579 logic cells;
● On-Board M25P80 SPI Flash ， 1M bytes for user configuration code;
● On-Board 256MB Micron DDR3, MT41J128M16JT-125
● On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC
● XC6SLX16 development board has two 64p, 2.54mm pitch headers for extending user IOs.
● All IOs are precisely designed with length matching
● XC6SLX16 development board has 3 user switches
● XC6SLX16 development board has 4 user LEDs;
● XC6SLX16 development board has JTAG interface, by using 6p, 2.54mm pitch header;
● XC6SLX16 development board PCB size is: 6.7cm x 8.4cm;
● Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
JTAG Interface –To Program FPGA & UART TO
USB
 PIN DETAILS
PIN NO DESCRIPTION PIN NO DESCRIPTION PIN NO DESCRIPTION
1 GND 11 F13 21 K12
2 VCC 12 G14 22 M16
3 GND 13 H16 23 N16
4 E13 14 G11 24 M14
5 B16 15 H14 25 C13
6 C16 16 J16 26 P16
7 D16 17 J12 27 R16
8 E16 18 J13 28 T15
9 F16 19 K16 29 T14
10 F12 20 L14 30 R12
31 GND
32 VCC
WHAT IS UART
● Universal asynchronous receiver and tranmitter
● Serial port, COM port, RS232, RS485
● VERY COMMON AND SIMPLE
● Useful for communication to
○ Microcontroller

○ Computer

○ Other FPGA
Asynchronous Vs Synchronous
UART
UART PARAMETERS
● Baud Rate (9600, 19200, 115200, others)
● Number of Data Bits (7, 8)
● Parity Bit (On, Off)
● Stop Bits (0, 1, 2)
● Flow Control (None, On, Hardware)
UART DATA STREAM EXAMPLE
ASCII TABLE –HEX
CIRCUIT DIAGRAM FOR UART
VHDL CODE -UART
● Print – “HELLO WORLD” in UART
● Two ports ( CLOCK as input ,TXD pin as output)
● Define two process

○ Baud clock generator

○ Transmit Data
●
Library and Port Declaration
--Library Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Entity Declaration
entity uart is
--Port Declaration
Port ( clk : in STD_LOGIC;
txd : out STD_LOGIC);
end uart;
UART TIMING DIAGRAM
Declaration
--Signal declaration
type state is( ready ,start, stop);
--ARRAY DECLARATION
type arr is array (1 to 13) of std_logic_vector(7 downto 0);
--PRESENT STATE
signal present_state :state := ready ;
--STORE The Individual Byte value to be send
signal store : std_logic_vector (7 downto 0);
--Baud clock declaration
signal baud_clk : std_logic;
--HELLO WORLD
constant str : arr := (X"48",X"65",X"6C",X"6C",X"6F",X"20",X"57",X"6F",X"72",X"6C",X"64",X"21",X"0D");
Baud clock generation
process (clk)
variable baud_count :integer range 0 to 325 :=0;
begin
if clk'event and clk ='1' then
if baud_count =325 then
baud_clk<= '1' ;
baud_count :=0;
else
baud_count :=baud_count+1;
baud_clk<= ‘0' ;
end if;
end if;
end process;
Present state : Ready
process (baud_clk)
variable i,k : integer := 0;
variable j : integer :=1;
begin
if baud_clk' event and baud_clk = '1' then
--Ready
if present_state = ready then
i:=i+1;
if i=8 then
txd<='0';
i:=0;
present_state<=start;
end if;
end if;
---Start
--Stop
Present state : Start
if present_state = start then if i=96 then
i:=i+1; txd<=store(5);
store<=str(j) (7 downto 0); end if ;
if i=16 then if i=112 then
txd<=store(0); txd<=store(6);
end if ; end if ;
if i=32 then if i=128 then
txd<=store(1); txd<=store(7);
end if ; end if ;
if i=48 then if i=144 then
txd<=store(2); txd<='1' ;--stop bit
end if ; end if ;
if i=64 then if i=160 then
txd<=store(3); i:=0;
end if ; present_state <= stop;
if i= 80 then end if ;
txd<=store(4); end if;
end if ;
Present state : stop
if present_state = stop then
if j=13 then
present_state <= stop;
j:=0;
else
present_state <= ready;
j:=j+1;
end if;
end if;
end if;
end process;
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