Module-2

Combinational Logic & Sequential Logic

Syllabus
 Introduction
• Logic circuits for digital • Sequential circuits employ
systems may be combinational storage elements in addition
or sequential. to logic gates.
• A combinational circuit • Their outputs are a function of
consists of logic gates whose the inputs and the state of the
outputs at any time are storage elements.
determined from only the • Because the state of the
present combination of inputs. storage elements is a function
• A combinational circuit of previous inputs, the outputs
performs an operation that of a sequential circuit depend
can be specified logically by a not only on present values of
set of Boolean functions. inputs, but also on past inputs,
and the circuit behavior must
be specified by a time
sequence of inputs and
internal states.
 Combinational Circuits
• A combinational circuit consists of an
interconnection of logic gates.
• Combinational logic gates react to the values
of the signals at their inputs and produce the
value of the output signal, transforming binary
information from the given input data to a
required output data. A block diagram of a
combinational circuit is shown in Fig.
• The n input binary variables
come from an external source;
• The m output variables are
produced by the internal
combinational logic circuit and
go to an external destination.
• Each input and output variable
exists physically as an analog
signal whose values are
interpreted to be a binary
signal that represents logic 1
and logic 0.
• For n input variables, there are 2n possible combinations
of the binary inputs.
• For each possible input combination, there is one
possible value for each output variable. Thus, a
combinational circuit can be specified with a truth table
that lists the output values for each combination of
input variables.
• A combinational circuit also can be described by m
Boolean functions, one for each output variable. Each
output function is expressed in terms of the n input
variables.
• Several combinational circuits , such as
adders, subtractors, comparators, decoders,
encoders, and multiplexers are available in
integrated circuits as medium-scale
integration (MSI) circuits, very largescale
integrated (VLSI) circuits and application-
specific integrated circuits (ASICs).
 Design Procedure
The design procedure of combinational circuits involves the
following steps:
1. From the specifications of the circuit, determine the
required number of inputs and outputs and assign a
symbol to each.
2. Derive the truth table that defines the required
relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output
as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the
design (manually or by simulation).
• Code Conversion Example
 A binary adder–subtractor
• A binary adder–subtractor is a combinational
circuit that performs the arithmetic operations
of addition and subtraction with binary
numbers.
• A combinational circuit that performs the
addition of two bits is called a half adder .
• One that performs the addition of three bits
(two significant bits and a previous carry) is a
full adder .
 Half Adder
• this circuit needs two binary
inputs and two binary outputs.
• We assign symbols x and y to
the two inputs and S (for sum)
and C (for carry) to the outputs.
• The truth table for the half
adder is listed in Table.
• The C output is 1 only when
both inputs are 1.
• The S output represents the
least significant bit of the sum.
 Full Adder
• A full adder is a combinational circuit that forms the arithmetic sum
of three bits.
• It consists of three inputs and two outputs. Two of the input
variables, denoted by x and y , represent the two significant bits to
be added. The third input, z , represents the carry from the previous
lower significant position.
• Two outputs are necessary because the arithmetic sum of three
binary digits ranges in value from 0 to 3, and binary representation
of 2 or 3 needs two bits. The two outputs are designated by the
symbols S for sum and C for carry.
• The binary variable S gives the value of the least significant bit of the
sum. The binary variable C gives the output carry formed by adding
the input carry and the bits of the words
Implementation of full adder with two half
adders and an OR gate
• The S output from the second half adder is the
exclusive-OR of z and the output of the first
half adder, giving
 Binary Adder
• A binary adder is a digital circuit that produces
the arithmetic sum of two binary numbers.
• It can be constructed with full adders
connected in cascade, with the output carry
from each full adder connected to the input
carry of the next full adder in the chain.
• Addition of n-bit numbers requires a chain of
n full adders or a chain of one-half adder and
n 9 1 full adders
• To demonstrate with a specific example, consider the two
binary numbers A = 1011 and B = 0011.
• Their sum S = 1110 is formed with the four-bit adder as
follows:
Carry Propagation
• The addition of two binary numbers in parallel implies that all the bits of
the augend and addend are available for computation at the same time.
• As in any combinational circuit, the signal must propagate through the
gates before the correct output sum is available in the output terminals.
• The total propagation time is equal to the propagation delay of a typical
gate, times the number of gate levels in the circuit.
• The longest propagation delay time in an adder is the time it takes the
carry to propagate through the full adders.
• Since each bit of the sum output depends on the value of the input carry,
the value of Si at any given stage in the adder will be in its steady-state
final value only after the input carry to that stage has been propagated.
• Inputs A3 and B3 are available as soon as input signals are
applied to the adder.
• However, input carry C3 does not settle to its final value until C2
is available from the previous stage.
• Similarly, C2 has to wait for C1 and so on down to C0.
• Thus, only after the carry propagates and ripples through all
stages will the last output S3 and carry C4 settle to their final
correct value.
• The circuit is redrawn with different labels in Fig. for convenience.
• The signals at Pi and Gi settle to their steady-state values after
they propagate through their respective gates.
• These two signals are common to all half adders and depend on
only the input augend and addend bits.
• The signal from the input carry Ci to the output carry Ci+1
propagates through an AND gate and an OR gate, which constitute
two gate levels.
• If there are four full adders in the adder, the output carry C4
would have 2 * 4 = 8 gate levels from C0 to C4.
• For an n -bit adder, there are 2*n gate levels for the carry to
propagate from input to output.
• Gi is called a carry generate , and it
produces a carry of 1 when both Ai and
Bi are 1, regardless of the input carry Ci
• Pi is called a carry propagate , because
it determines whether a carry into
stage i will propagate into stage i + 1
• The carry propagation time is an important
attribute of the adder because it limits the
speed with which two numbers are added.
• Since all other arithmetic operations are
implemented by successive additions, the time
consumed during the addition process is critical.
• An obvious solution for reducing the carry
propagation delay time is to employ faster gates
with reduced delays.
• We now write the Boolean functions for the
carry outputs of each stage and substitute the
value of each Ci from the previous equations:
Carry-look ahead adder
 Binary Subtractor
• The subtraction A - B can be done by taking
the 2’s complement of B and adding it to A .
• The 2’s complement can be obtained by taking
the 1’s complement and adding 1 to the least
significant pair of bits.
• The 1’s complement can be implemented with
inverters, and a 1 can be added to the sum
through the input carry.
• The addition and subtraction operations can be combined into
one circuit with one common binary adder by including an
exclusive-OR gate with each full adder.
• The mode input M controls the operation. When M = 0, the
circuit is an adder, and when M = 1, the circuit becomes a
subtractor.
• Each exclusive-OR gate receives input M and one of the inputs
of B .
• When M = 0, we have B XOR 0 = B. The full adders receive the
value of B , the input carry is 0, and the circuit performs A plus
B.
• When M = 1, we have B XOR 1 = B and C0 = 1. The B inputs are
all complemented and a 1 is added through the input carry.
The circuit performs the operation A plus the 2’s complement
of B .
• If the two binary numbers are considered to be unsigned, then
the C bit detects a carry after addition or a borrow after
subtraction.
• If the numbers are considered to be signed, then the V bit
detects an overflow.
• If V = 0 after an addition or subtraction, then no overflow
occurred and the n -bit result is correct.
• If V = 1, then the result of the operation contains n + 1 bits, but
only the rightmost n bits of the number fit in the space
available, so an overflow has occurred.
• The (n + 1)th bit is the actual sign and has been shifted out of
position.
Overflow
• When two numbers with n digits each are
added and the sum is a number occupying n +
1 digits, we say that an overflow occurred.
• Overflow is a problem in digital computers
because the number of bits that hold the
number is finite and a result that contains n +
1 bits cannot be accommodated by an n -bit
word.
• The detection of an overflow after the addition of two
binary numbers depends on whether the numbers are
considered to be signed or unsigned.
• When two unsigned numbers are added, an overflow is
detected from the end carry out of the most significant
position.
• In the case of signed numbers, two details are important:
– the leftmost bit always represents the sign, and negative
numbers are in 2’s-complement form.
– When two signed numbers are added, the sign bit is treated as
part of the number and the end carry does not indicate an
overflow.
• An overflow cannot occur after an addition if one number
is positive and the other is negative, since adding a positive
number to a negative number produces a result whose
magnitude is smaller than the larger of the two original
numbers.
• An overflow may occur if the two numbers added are both
positive or both negative.
• An overflow condition can be detected by
observing the carry into the sign bit position
and the carry out of the sign bit position. If
these two carries are not equal, an overflow
has occurred.
 Decoder
• A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n
unique output lines.
• If the n -bit coded information has unused combinations,
the decoder may have fewer than 2n outputs.
• The decoders presented here are called n -to- m -line
decoders, where m<=2n . Their purpose is to generate
the 2n (or fewer) minterms of n input variables.
• Each combination of inputs will assert a unique output.
three-to-eight-line decoder circuit
• The three inputs are decoded into eight outputs, each
representing one of the minterms of the three input variables.
• The three inverters provide the complement of the inputs, and
each one of the eight AND gates generates one of the minterms.
• A particular application of this decoder is binary-to-octal
conversion.
• The input variables represent a binary number, and the outputs
represent the eight digits of a number in the octal number system.
• However, a three-to-eight-line decoder can be used for decoding
any three-bit code to provide eight outputs, one for each element
of the code
• Some decoders are
constructed with NAND gates.
• A two-to-four-line decoder
with an enable input
constructed with NAND gates
is shown in Fig.
• The circuit operates with
complemented outputs and a
complement enable input.
• The decoder is enabled when
E is equal to 0 (i.e., active-low
enable).
• As indicated by the truth table, only one
output can be equal to 0 at any given time; all
other outputs are equal to 1.
• The output whose value is equal to 0
represents the minterm selected by inputs A
and B .
• The circuit is disabled when E is equal to 1,
regardless of the values of the other two
inputs.
• In general, a decoder may operate with complemented or
uncomplemented outputs.
• The enable input may be activated with a 0 or with a 1
signal.
• Some decoders have two or more enable inputs that must
satisfy a given logic condition in order to enable the circuit.
• A decoder with enable input can function as a
demultiplexer— a circuit that receives information from a
single line and directs it to one of 2n possible output lines.
• The selection of a specific output is controlled by the bit
combination of n selection lines.
• Decoders with enable inputs • When w 1, the enable
can be connected together to conditions are reversed: The
form a larger decoder circuit. bottom decoder outputs
• Figure shows two 3-to-8-line generate minterms 1000 to
decoders with enable inputs 1111, while the outputs of
connected to form a 4-to-16- the top decoder are all 0’s.
line decoder. • Enable inputs are a
• When w=0, the top decoder is convenient feature for
enabled and the other is interconnecting two or more
disabled. The bottom decoder standard components for the
outputs are all 0’s, and the top purpose of combining them
eight outputs generate into a similar function with
minterms 0000 to 0111.
more inputs and outputs.
 Combinational Logic Implementation
• A decoder provides the 2n minterms of n input variables.
• Each output of the decoder is associated with a unique
pattern of input bits.
• A decoder that generates the minterms of the function,
together with an external OR gate that forms their logical
sum, provides a hardware implementation of the
function.
• In this way, any combinational circuit with n inputs and m
outputs can be implemented with an n -to-2n-line
decoder and m OR gates.
MULTIPLEXERS
Boolean Function Implementation
F (A, B, C, D) = ∑ (1, 3, 4, 11, 12, 13, 14, 15)