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Cache

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18 views22 pages

Cache

Uploaded by

muthusaran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CACHE

AGENDA
 Simple overview on cache
 Types of cache

 Usage of cache

 Few cache Algorithms


CACHE
 Small amount of fast memory
 Sits between normal main memory and CPU

 May be located on CPU chip or module

Client Cache Storage


THE IDEA OF USING CACHING
 Using very short time to access the recently and
frequently data

cache: fast but expensive disks: cheap but slow


TYPE OF CACHE

 CPU cache
 Disk cache

 Other caches

Proxy web cache


USAGE OF CACHING
 Caching is used widely in:
 Storage systems
 Databases
 Web servers
 Middleware
 Processors
 Operating systems
 RAID controller
 Many other applications
CACHE MEMORY STRUCTURE
CACHE OPERATION – OVERVIEW
 CPU requests contents of memory location
 Check cache for this data

 If present, get from cache (fast)

 If not present, read required block from main memory to


cache
 Cache includes tags to identify which block of main
memory is in each cache slot
CACHE DESIGN
 Size
 Algorithm

 Write Policy

 Block Size

 Number of Caches
SIZE DOES MATTER
 Cost
 More cache is expensive
 Speed
 More cache is faster (up to a point)
 Checking cache for data takes time
TYPICAL CACHE ORGANIZATION

Bus
Client Cache Storage

Client
Cache Storage
READ CACHE HIT
When the cache client needs to access a datum , it first checks
the cache. If an entry can be found with a tag matching that
of the desired datum, the datum in the entry is used instead.
This situation is known as a cache hit

Client Cache Storage


READ CACHE MISS
When the cache client needs to access a datum , it first checks
the cache. If an entry can not be found with a tag matching
that of the desired datum. This situation is known as a cache
miss.

Client Cache Storage


CACHE ALGORITHMS
 Famous algorithms
 LRU (Least Recently Used)
 LFU (Least Frequently Used)

 Not so Famous algorithms


 LRU –K
 2Q
 FIFO
 others
LRU (LEAST RECENTLY USED)
 LRU is implemented by a linked list.
 Discards the least recently used items first.
LFU (LEAST FREQUENTLY USED)
 Counts, how often an item is needed. Those that are used
least often are discarded first.
DISADVANTAGES
 LRU – problem with process scans a huge database

 LFU – process scans a huge database, but it made the


performance even worse.
WRITE POLICY
 Must not overwrite a cache block unless main memory is
up to date
 Multiple CPUs may have individual caches

 I/O may address main memory directly


WRITE THROUGH
 All writes go to main memory as well as cache
 Lots of traffic

 Slows down writes


WRITE BACK
 Updates initially made in cache only
 Update bit for cache slot is set when update occurs

 If block is to be replaced, write to main memory only if


update bit is set
COMPARISON OF CACHE SIZES
Year of
Processor Type L1 cachea L2 cache L3 cache
Introduction
IBM 360/85 Mainframe 1968 16 to 32 KB — —
PDP-11/70 Minicomputer 1975 1 KB — —
VAX 11/780 Minicomputer 1978 16 KB — —
IBM 3033 Mainframe 1978 64 KB — —
IBM 3090 Mainframe 1985 128 to 256 KB — —
Intel 80486 PC 1989 8 KB — —
Pentium PC 1993 8 KB/8 KB 256 to 512 KB —
PowerPC 601 PC 1993 32 KB — —
PowerPC 620 PC 1996 32 KB/32 KB — —
PowerPC G4 PC/server 1999 32 KB/32 KB 256 KB to 1 MB 2 MB
IBM S/390 G4 Mainframe 1997 32 KB 256 KB 2 MB
IBM S/390 G6 Mainframe 1999 256 KB 8 MB —
Pentium 4 PC/server 2000 8 KB/8 KB 256 KB —
High-end server/
IBM SP 2000 64 KB/32 KB 8 MB —
supercomputer
CRAY MTAb Supercomputer 2000 8 KB 2 MB —
Itanium PC/server 2001 16 KB/16 KB 96 KB 4 MB
SGI Origin 2001 High-end server 2001 32 KB/32 KB 4 MB —
Itanium 2 PC/server 2002 32 KB 256 KB 6 MB
IBM POWER5 High-end server 2003 64 KB 1.9 MB 36 MB
CRAY XD-1 Supercomputer 2004 64 KB/64 KB 1MB —
Thank You

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