Lecture 9

Virtual Memory

Acknowledgement: These slides are based on the textbook

(Computer Systems: A Programmer’s Perspective) and its slides. 1
 Multiprocessing: The Reality
Memory
Stack Stack Stack
Heap Heap Heap
Data Data … Data
Code Code Code
Saved Saved Saved
registers registers registers

CPU
Registers

 Single processor executes multiple processes concurrently

 Process executions interleaved (multitasking)
 Address spaces managed by virtual memory system (in our next lecture)
 Register values for nonexecuting processes saved in memory
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 2
The problem
• The program image is too large to be fit into the main memory

0100 A
0101 B
0102 C
0103 D
0104 E
0105 F
0106 G
？
0107 H

…
…
Main memory
…

……
A large program
3
Basic idea: paging
• Chunk the program image into virtual pages
• Chunk the main memory into physical pages, also called frames
• Each time, load a page into a specific frame of the main memory
00 A
B
Page 0 C
D
04 E
F Frame 0
Page 1 G
H
08 I
Frame 1
J
Page 2 K
L
0C M
N
Page 3 O
P
4
Basic idea: paging
• Each time, load a page into a frame of the main memory

00 A
B
Page 0 C
D
0100 A
04 E B
F C Frame 0
Page 1 G D
H
0104
08 I
Frame 1
J
Page 2 K
L
0C M
N
Page 3 O
P
5
 Why Virtual Memory (VM)?

 Uses main memory efficiently

 Use DRAM as a cache for parts of a virtual address space

 Simplifies memory management

 Each process gets the same uniform linear address space

 Isolates address spaces

 One process can’t read/write another process’s memory

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 6

 Outline
 Address spaces

 VM as a tool for caching

 VM as a tool for memory management

 VM as a tool for memory protection

 Address translation
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 7
 A System Using Physical Addressing
Main memory
0:
1:
Physical address 2:
(PA) 3:
CPU 4:
4
5:
6:
7:
8:

...
M-1:

Data word

 Used in “simple” systems

 E.g., embedded microcontrollers in devices like
cars, elevators, and digital picture frames
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 8
 A System Using Virtual Addressing
Main memory
0:
CPU Chip 1:
2:
Virtual address Physical address
(VA) Memory (PA) 3:
CPU management 4:
4100 unit (MMU) 4 5:
6:
7:
8:

...
M-1:

Data word

 Used in all modern servers, laptops, and smart phones

 An important concept for virtual memory (see the following
slides)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 9
 Address Spaces
 Linear address space: consecutive non-negative integer addresses:
{0, 1, 2, 3 … }

 Virtual address space: use n-bit integers as virtual addresses,

total N = 2n virtual addresses:
{0, 1, 2, 3, …, N-1}

 Physical address space: use m-bit integers as physical addresses,

total M = 2m physical addresses:
{0, 1, 2, 3, …, M-1}

 In general, N is larger than M

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 10

 Outline
 Address spaces

 VM as a tool for caching

 VM as a tool for memory management

 VM as a tool for memory protection

 Address translation
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 11
 VM as a Tool for Caching
 Conceptually, virtual memory is an array of N consecutive
bytes stored on disk
 The contents of the array on disk are cached in physical
memory (DRAM cache)
 These cache blocks are called pages (size is P = 2p bytes)
Virtual memory Physical memory
0
VP 0 Unallocated
0
VP 1 Cached Empty PP 0
Uncached PP 1
Unallocated Empty
Cached
Uncached Empty
Cached PP 2m-p-1
M-1
VP 2n-p-1 Uncached
N-1

Virtual pages (VPs) Physical pages (PPs)

stored on disk cached in DRAM

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 12

 DRAM Cache Organization
 DRAM cache organization driven by the enormous
miss penalty
 Disk is about 10,000x slower than DRAM
 Consequences
 Large page (block) size: typically 4 KB to 4 MB
 Fully associative
 Any virtual page (VP) can be placed in any physical page (PP)
 Sophisticated replacement algorithms for DRAM cache
 Beyond the scope of this course
 Write-back
 Writes are not immediately performed in the disk
 Write to the disk when a page is evicted from DRAM cache

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 13

 Enabling Data Structure: Page Table
 Page table: an array of page table entries (PTEs) that maps
virtual pages to physical pages
 Per-process kernel data structure in DRAM
Physical memory
Physical page (DRAM)
number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
VP 6
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition VP 7 14
 Page Hit
 Page hit: reference to VM word that is in physical memory
(DRAM cache hit)
Physical memory
Physical page (DRAM)
Virtual address
number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 15
 Page Fault
 Page fault: reference to VM word that is not in physical
memory (DRAM cache miss)
Physical memory
Physical page (DRAM)
Virtual address number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 16
 Handling Page Fault
 1. Page miss causes page fault (an exception)

Physical memory
Physical page (DRAM)
Virtual address number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 17
 Handling Page Fault
 1. Page miss causes page fault (an exception)
 2. Page fault handler selects a victim to be evicted (here VP 4)
Physical memory
Physical page (DRAM)
Virtual address number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 18
 Handling Page Fault
 1. Page miss causes page fault (an exception)
 2. Page fault handler selects a victim to be evicted (here VP 4)
Physical memory
Physical page (DRAM)
Virtual address number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 3 PP 3
1
1
0
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 19
 Handling Page Fault
 1. Page miss causes page fault (an exception)
 2. Page fault handler selects a victim to be evicted (here VP 4)
 3. Offending instruction is restarted: page hit!
Physical memory
Physical page (DRAM)
Virtual address number or
VP 1 PP 0
Valid disk address
VP 2
PTE 0 0 null
VP 7
1 VP 3 PP 3
1
1
0
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table
VP 3
(DRAM)
VP 4
Demand paging: Waiting until the miss VP 6
to copy the page to DRAM
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 20
 Locality to the Rescue Again!
 Virtual memory works efficiently because of locality
 At any point in time, programs tend to access a set of active
virtual pages called the working set
 Programs with better temporal locality will have smaller working sets

 If (working set size < main memory size)

 Good performance for one process after compulsory misses

 If ( SUM(working set sizes) > main memory size )

 Thrashing: Performance meltdown where pages are swapped (copied)
in and out continuously

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 21

 Outline
 Address spaces

 VM as a tool for caching

 VM as a tool for memory management

 VM as a tool for memory protection

 Address translation
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 22
 VM as a Tool for Memory Management
 Key idea: each process has its own virtual address space
 It can view memory as a simple linear array
 Mapping function scatters addresses through physical memory

0 Address 0
Physical
Virtual
Address VP 1
translation Address
Space for VP 2 PP 2 Space
Process 1: ... (DRAM)
N-1
(e.g., read-only
PP 6 library code)
0
Virtual PP 8
Address VP 1
Space for VP 2
Process 2: ... ...
N-1 M-1
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 23
 VM as a Tool for Memory Management
 Simplifying memory allocation
 Each virtual page can be mapped to any physical page
 A virtual page can be stored in different physical pages at different times
 Sharing code and data among processes
 Map virtual pages to the same physical page (here: PP 6)
0 Address 0
Physical
Virtual
Address VP 1
translation Address
Space for VP 2 PP 2 Space
Process 1: ... (DRAM)
N-1
(e.g., read-only
PP 6 library code)
0
Virtual PP 8
Address VP 1
Space for VP 2
Process 2: ... ...
N-1 M-1
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 24
 Outline
 Address spaces

 VM as a tool for caching

 VM as a tool for memory management

 VM as a tool for memory protection

 Address translation
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 25
 VM as a Tool for Memory Protection
 Extend page table entries (PTEs) with permission
bits
 Memory management unit (MMU) checks these bits
on each access Physical
Process i: SUP READ WRITE EXEC Address Address Space
VP 0: No Yes No Yes PP 6
VP 1: No Yes Yes Yes PP 4
VP 2: PP 2
Yes Yes Yes No PP 2
•
• PP 4
•
PP 6
Process j: SUP READ WRITE EXEC Address
PP 8
VP 0: No Yes No Yes PP 9 PP 9
VP 1: Yes Yes Yes Yes PP 6
VP 2: No Yes Yes Yes PP 11 PP 11

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 26

 Outline
 Address spaces

 VM as a tool for caching

 VM as a tool for memory management

 VM as a tool for memory protection

 Address translation
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 27
 VM Address Translation
 Virtual Address Space
 V = {0, 1, …, N–1}
 Physical Address Space
 P = {0, 1, …, M–1}
 Address Translation
 MAP: V  P U {}
 For virtual address a:
 MAP(a) = a’
if data at virtual address a is at physical address a’ in
P
 MAP(a) = 
if data at virtual address a is not in physical memory
– Either invalid or stored on disk
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 28
 Summary of Address Translation Symbols
 Basic Parameters
 N = 2n : Number of addresses in virtual address space
 M = 2m : Number of addresses in physical address space
 P = 2p : Page size (bytes)
 Components of the virtual address (VA)
 TLBI: TLB index
 TLBT: TLB tag
 VPO: Virtual page offset
 VPN: Virtual page number
 Components of the physical address (PA)
 PPO: Physical page offset (same as VPO)
 PPN: Physical page number
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 29
 Address Translation With a Page Table
Virtual address
n-1 p p-1 0
Page table
base register Virtual page number (VPN) Virtual page offset (VPO)
(PTBR)

Page table
Valid Physical page number (PPN)
Physical page table
address for the current
process

Valid bit = 0:
Page not in memory
Valid bit = 1
(page fault)

m-1 p p-1 0
Physical page number (PPN) Physical page offset (PPO)
Physical address

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 30

 Address Translation: Page Hit
2
CPU Chip PTEA
1
PTE
VA
CPU MMU 3
Cache/
PA Memory
4

Data
5

1) Processor sends virtual address to MMU

2-3) MMU fetches PTE from page table in memory
4) MMU sends physical address to cache/memory
5) Cache/memory sends data word to processor

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 31

 Address Translation: Page Fault
Exception
Page fault handler
4

2
CPU Chip PTEA Victim page
1
5
VA PTE Cache/
CPU MMU Disk
7 3 Memory
New page
6

1) Processor sends virtual address to MMU

2-3) MMU fetches PTE from page table in memory
4) Valid bit is zero, so MMU triggers page fault exception
5) Handler identifies victim (and, if dirty, pages it out to disk)
6) Handler pages in new page and updates PTE in memory
7) Handler returns to original process, restarting faulting instruction
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 32
 Summary
 Programmer’s view of virtual memory
 Each process has its own private linear address space
 Cannot be corrupted by other processes

 System view of virtual memory

 Uses memory efficiently by caching virtual memory pages
Efficient only because of locality

 Simplifies memory management and programming
 Simplifies protection by providing a convenient inter-
positioning point to check permissions

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 33