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Frequency Divider by Odd Using Verilog Code

The document discusses designing an odd number frequency divider circuit that can output a 50% duty cycle. It presents a simple odd number frequency divider circuit consisting of a general odd number counter and a duty cycle trimming circuit with only six additional transistors. The document also includes a Verilog code example of a frequency divider module and a testbench.

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119 views

Frequency Divider by Odd Using Verilog Code

The document discusses designing an odd number frequency divider circuit that can output a 50% duty cycle. It presents a simple odd number frequency divider circuit consisting of a general odd number counter and a duty cycle trimming circuit with only six additional transistors. The document also includes a Verilog code example of a frequency divider module and a testbench.

Uploaded by

ece19637ec003
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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INTRODUCTION TO A FREQUENCY

DIVIDER BY USING AN ODD


NUMBER
FREQUENCY DIVIDER BY ODD NUMBER
• Frequency or clock dividers are among the most common circuits
used in digital systems.
• Somehow dividing the frequency with an odd number is not that
easy.
• Designing an frequency divider by even number is easy
• A simple odd number frequency divider with 50% duty cycle is
presented. The odd number frequency divider consists of a general odd
number counter and the proposed duty cycle trimming circuit. The duty
cycle trimming circuit can output 50% duty cycle with only additional six
transistors.
circuit diagram of frequency divider
Verilog code
module clk_div3(clk,reset, clk_out);

input clk;
input reset;
output clk_out;

reg [1:0] pos_count, neg_count;


wire [1:0] r_nxt;

always @(posedge clk)


if (reset)
pos_count <=0;
else if (pos_count ==2) pos_count <= 0;
else pos_count<= pos_count +1;

always @(negedge clk)


if (reset)
neg_count <=0;
else if (neg_count ==2) neg_count <= 0;
else neg_count<= neg_count +1;

assign clk_out = ((pos_count == 2) | (neg_count == 2));


endmodule
Testbench for frequency divider
module clkdiv3_tb;
reg clk,reset;
wire clk_out;

clk_div3 t1(clk,reset,clk_out);
initial
clk= 1'b0;
always
#5 clk=~clk;
initial
begin
#5 reset=1'b1;
#10 reset=1'b0;
#100 $finish;
end

initial
$monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);

initial
begin
$dumpfile("clkdiv3_tb.vcd");
$dumpvars(0,clkdiv3_tb);
end
endmodule
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