UNIT-5: Memory

Management

Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne

 Background
 Program must be brought (from disk)
into memory and placed within a
process for it to be run
 Main memory and registers are only
storage CPU can access directly
 Cache sits between main memory
and CPU registers
 Protection of memory required to
ensure correct operation

Operating System Concepts – 8th Edition 8.2 Silberschatz, Galvin and Gagne
 Base and Limit Registers
 A pair of base and limit registers define the
logical address space

Operating System Concepts – 8th Edition 8.3 Silberschatz, Galvin and Gagne
 Logical vs. Physical Address Space
 The concept of a logical address space that is bound to
a separate physical address space is central to proper
memory management.

 Logical address – generated by the CPU; also referred

to as virtual address.

 Physical address – address seen by the memory unit

and Program is called absolute code.

 Address Binding: Mapping Logical addresses into

physical addresses.

Operating System Concepts – 8th Edition 8.4 Silberschatz, Galvin and Gagne
 Binding of Instructions and Data to Memory
 Address binding of instructions and data to
memory addresses can happen at three different
stages
 Compile time: If memory location known a
priori, absolute code can be generated.

 Load time: Loader must generate relocatable

code if memory location is not known at
compile time.

 Execution time: Binding delayed until run

time Need hardware support for address
maps (e.g., base and limit registers)

Operating System Concepts – 8th Edition 8.5 Silberschatz, Galvin and Gagne
 Multistep Processing of a User Program

Operating System Concepts – 8th Edition 8.6 Silberschatz, Galvin and Gagne
 Memory-Management Unit (MMU)

 Hardware device that maps virtual

to physical address
 In MMU scheme, the value in the
relocation register is added to every
address generated by a user process
at the time it is sent to memory
 The user program deals with logical
addresses; it never sees the real
physical addresses

Operating System Concepts – 8th Edition 8.7 Silberschatz, Galvin and Gagne
 Dynamic relocation using a
relocation register

Operating System Concepts – 8th Edition 8.8 Silberschatz, Galvin and Gagne
 Dynamic Loading

 Routine is not loaded until it is called

 Better memory-space utilization;
unused routine is never loaded
 Useful when large amounts of code
are needed to handle infrequently
occurring cases
 No special support from the
operating system is required
implemented through program design

Operating System Concepts – 8th Edition 8.9 Silberschatz, Galvin and Gagne
 Dynamic Linking
 Linking postponed until execution time
 Small piece of code, stub, used to
locate the appropriate memory-
resident library routine
 Stub replaces itself with the address of
the routine, and executes the routine
 Operating system needed to check if
routine is in processes’ memory
address
 Dynamic linking is particularly useful
for libraries
 System also known as shared libraries
Operating System Concepts – 8th Edition 8.10 Silberschatz, Galvin and Gagne
 Swapping
 A process can be swapped temporarily out of
memory to a backing store, and then brought back
into memory for continued execution
 Backing store – fast disk large enough to
accommodate copies of all memory images for all
users; must provide direct access to these memory
images
 Roll out, roll in – swapping variant used for priority-
based scheduling algorithms; lower-priority process
is swapped out so higher-priority process can be
loaded and executed
 Major part of swap time is transfer time; total
transfer time is directly proportional to the amount
of memory swapped
 Modified versions of swapping are found on many
systems (i.e., UNIX, Linux, and Windows)

Operating System Concepts – 8th Edition 8.11 Silberschatz, Galvin and Gagne
 Schematic View of Swapping

Operating System Concepts – 8th Edition 8.12 Silberschatz, Galvin and Gagne
 Contiguous Allocation
 Main memory usually into two partitions:
 Resident operating system, usually held in
low memory with interrupt vector
 User processes that held in high memory
 Relocation registers used to protect user
processes from each other, and from
changing operating-system code and data
 Base register contains value of smallest
physical address
 Limit register contains range of logical
addresses – each logical address must be
less than the limit register
 MMU maps logical address dynamically
Operating System Concepts – 8th Edition 8.13 Silberschatz, Galvin and Gagne
 Hardware Support for Relocation
and Limit Registers

Operating System Concepts – 8th Edition 8.14 Silberschatz, Galvin and Gagne
 Contiguous Allocation (Cont.)

 Multiple-partition allocation
 Hole – block of available memory; holes of
various size are scattered throughout memory
 When a process arrives, it is allocated memory
from a hole large enough to accommodate it
 Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS OS OS OS
process process process process
5 5 5 5
process process
9 9
process process
8 10

process process process process

2 2 2 2

Operating System Concepts – 8th Edition 8.15 Silberschatz, Galvin and Gagne
 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of
free holes
 First-fit: Allocate the first hole that is big enough
 Best-fit: Allocate the smallest hole that is big enough;
must search entire list, unless ordered by size
 Produces the smallest leftover hole
 Worst-fit: Allocate the largest hole; must also search
entire list, produces the largest leftover hole

Operating System Concepts – 8th Edition 8.16 Silberschatz, Galvin and Gagne
 Fragmentation

 External Fragmentation – total memory space

exists to satisfy a request, but it is not contiguous

 Internal Fragmentation – allocated memory may be

slightly larger than requested memory; this size
difference is memory internal to a partition, but not
being used

 Reduce external fragmentation by compaction

 Shuffle memory contents to place all free

memory together in one large block

Operating System Concepts – 8th Edition 8.17 Silberschatz, Galvin and Gagne
 Paging
 Logical address space of a process can be non-
contiguous process is allocated physical memory
whenever the latter is available
 Divide physical memory into fixed-sized blocks
called frames.(between 512 bytes and 8,192 bytes)
 Divide logical memory into blocks of same size
called pages.(same size of frame)
 MMU Keep track of all free frames
 To run a program of size n pages, need to find n free
frames and load program
 Set up a page table to translate logical to physical
addresses
 Internal fragmentation is there, but no external
fragmentation.

Operating System Concepts – 8th Edition 8.18 Silberschatz, Galvin and Gagne
 Paging Model of Logical and
Physical Memory

Operating System Concepts – 8th Edition 8.19 Silberschatz, Galvin and Gagne
 Address Translation Scheme
 Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
 Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit.

m-n n
page number page offset
p d

Operating System Concepts – 8th Edition 8.20 Silberschatz, Galvin and Gagne
 Paging Example
32-byte logical memory and page size 4-bytes pages
(Frame number* page size)+ offset

Operating System Concepts – 8th Edition 8.21 Silberschatz, Galvin and Gagne
 Size of the page
If 2m bytes of storage is available and page size
is 2n bytes then
The size of the instruction is m bits.
The size of the page number takes m-n bits.
The size of the offset is n bits.
The size of the logical address is m bits.
Ex:
Lets say, there is 32 bytes of logical/physical
address space.(25, m=5 ie m bits is size of the
instruction) The page size is 4 bytes.(22, n=2)
Now
m=5, n=2 , so the page number needs 3 bits to
represent and 2 bits
p are needed
d to represent
offset.
Address of 011 11
Instruction p:
m-n =3 n=2
Operating System Concepts – 8th Edition 8.22 Silberschatz, Galvin and Gagne
 Implementation of Page Table
 Page table is kept in main memory, so CPU
needs two memory accesses page table and
other is data/instruction.

 Page-table base register(PTBR) points to the

page table from process.

 Page-table length register(PTLR) indicates size

of the page table.

 The two memory access takes longer time so

this problem can be solved by the use of a
special fast-lookup hardware cache called
associative memory or translation look-aside
buffers (TLBs).

Operating System Concepts – 8th Edition 8.23 Silberschatz, Galvin and Gagne
 Paging Hardware With TLB

Operating System Concepts – 8th Edition 8.24 Silberschatz, Galvin and Gagne
 Memory Protection
 Memory protection implemented by
associating protection bit with
each frame
 Valid-invalid bit attached to each
entry in the page table:
 “valid” indicates that the
associated page is in the
process’ logical address space,
and is thus a legal page
 “invalid” indicates that the page
is not in the process’ logical
address space
Operating System Concepts – 8th Edition 8.25 Silberschatz, Galvin and Gagne
 Valid (v) or Invalid (i)
Bit In A Page Table

Operating System Concepts – 8th Edition 8.26 Silberschatz, Galvin and Gagne
 Shared Pages Example

Operating System Concepts – 8th Edition 8.27 Silberschatz, Galvin and Gagne
 Structure of the Page Table

 The page table may beimplemented

in many ways.

 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables

Operating System Concepts – 8th Edition 8.28 Silberschatz, Galvin and Gagne
 Hierarchical Page Tables

 Break up the logical address

space into multiple page tables
 A simple technique is a two-level
page table

Operating System Concepts – 8th Edition 8.29 Silberschatz, Galvin and Gagne
 Two-Level Page-Table Scheme

Operating System Concepts – 8th Edition 8.30 Silberschatz, Galvin and Gagne
 Two-Level Paging Example
 A logical address (on 32-bit machine with 1K page
size) is divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits
 Since the page table is paged, the page number is
further divided into:
 a 12-bit page number
 a 10-bit page offset
 Thus, a logical address is as follows:

where pi is an index into the outer page table, and

p2 is the displacement within the page of the outer
page table page pi
number page offset
p2 d
1 1 1
2 0 0

Operating System Concepts – 8th Edition 8.31 Silberschatz, Galvin and Gagne
 Address-Translation Scheme

Operating System Concepts – 8th Edition 8.32 Silberschatz, Galvin and Gagne
 Hashed Page Tables

 Common in address spaces > 32 bits

 The virtual page number is hashed into
a page table
 This page table contains a chain of
elements hashing to the same
location
 Virtual page numbers are compared in
this chain searching for a match
 If a match is found, the corresponding
physical frame is extracted

Operating System Concepts – 8th Edition 8.33 Silberschatz, Galvin and Gagne
 Hashed Page Table

Operating System Concepts – 8th Edition 8.34 Silberschatz, Galvin and Gagne
 Inverted Page Table

 One entry for each real page of

memory
 Entry consists of the virtual address
of the page stored in that real memory
location, with information about the
process that owns that page
 Decreases memory needed to store
each page table, but increases time
needed to search the table when a
page reference occurs

Operating System Concepts – 8th Edition 8.35 Silberschatz, Galvin and Gagne
 Inverted Page Table Architecture

Operating System Concepts – 8th Edition 8.36 Silberschatz, Galvin and Gagne
 Segmentation

 Memory-management scheme that supports user

view of memory
 A program is a collection of segments
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Operating System Concepts – 8th Edition 8.37 Silberschatz, Galvin and Gagne
 User’s View of a Program

Operating System Concepts – 8th Edition 8.38 Silberschatz, Galvin and Gagne
 Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Operating System Concepts – 8th Edition 8.39 Silberschatz, Galvin and Gagne
 Segmentation Architecture
 Logical address consists of a two tuple:

<segment-number, offset>,
 Segment table – maps two-dimensional
physical addresses; each table entry has:
 base – contains the starting physical address
where the segments reside in memory
 limit – specifies the length of the segment
 Segment-table base register (STBR) points to
the segment table’s location in memory
 Segment-table length register (STLR) indicates
number of segments used by a program;
segment number s is legal if s <
STLR
Operating System Concepts – 8th Edition 8.40 Silberschatz, Galvin and Gagne
 Segmentation Architecture (Cont.)
 Protection
 With each entry in segment table
associate:
validation bit = 0  illegal segment
read/write/execute privileges
 Protection bits associated with segments;
code sharing occurs at segment level.
 Since segments vary in length, memory
allocation is a dynamic storage-allocation
problem.
 A segmentation example is shown in the
following diagram.
Operating System Concepts – 8th Edition 8.41 Silberschatz, Galvin and Gagne
 Segmentation Hardware

Operating System Concepts – 8th Edition 8.42 Silberschatz, Galvin and Gagne
 Example of Segmentation

Operating System Concepts – 8th Edition 8.43 Silberschatz, Galvin and Gagne
 End of Chapter 8

Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne