8051 Interrupts

Overview
• Interrupts are special signals through which other
processes and devices can request for CPU services.
• CPU services are provided by executing a certain peace of
code called ISR, Interrupt Service Routine or ISS Interrupt
Service Subroutine.
• Using interrupts, many operations can be controlled
simultaneously, without any large burden.
• An interrupt can be generated externally (from external
devices) or internally (by internal devices or software
instructions).
• Every processor has a set of rules to be followed when an
interrupt is recognized. However, a generalized sequence
of operation is listed next to get an idea.
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 Illustration of Interrupts

MAIN: ISR:
0500 MOV A,#21 t 2100 XCH A, R0
p
r ru
te
In

0510 ADD A, #50

0512 MOV R0,A Ba
ck
to
Ma
in
Return
2115 RETI
Address
053A SJMP $
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 IE: Interrupt Enable SFR
Byte Address: A8H

Bit Address AFH AEH ADH ACH ABH AAH A9H A8H

Bit No 7 6 5 4 3 2 1 0
Designation EA - - ES ET1 EX1 ET0 EX0

• EA – Enable all the bits when set to 1. Disable all

interrupts when cleared to 0 i.e. Master Disable.
• EX0/EX1 – Enable external interrupts INT0/INT1.
• ET0/ET1 – Enable Timer 0/ Timer 1 interrupts.
• ES – Enable serial port interrupt.

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 Interrupt Organization

EA

P3.2
INT 0 IE0 EX0 0003H

TIMER 0 TF0 ET0 000BH

P3.3
INT 1 IE1 EX1 0013H

TIMER 1 TF1 ET1 001BH

UART 0023H
RI/TI ES
TX / RX

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 Interrupt Vectored Table
• In 8051, all the interrupts are vectored interrupt and
the interrupts along with their vector addresses are
summarized in below Interrupt Vector Table.
Functional
Interrupt Vector Corresponding Flag
Name of Priority
Source Address SFR bit Clearing
SFR bit
INT0 0003H TCON.1 IE0 Auto 1
Timer 0
000BH TCON.5 TF0 Auto 2
Interrupt
INT1 0013H TCON.3 IE1 Auto 3
Timer 1
001BH TCON.7 TF1 Auto 4
Interrupt
Serial SCON.0 RI
0023H Manual 5
Interrupt SCON.1 TI

• Interrupt Vector Address for RESET is 0000H.

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 Experiment 1

Configure Timer 0 of 8051 in Mode 1 to generate

variable delays using interrupt with a resolution of 1
msec and complement the status of LED connected at
Pin P3.6 after every 5 seconds.

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 Experiment 1 (Contd.)

CONTROLLER RESET
TF=0 ISR BEGINS ; DEFINE FUNCTION as ISR.
RELOAD TIMER
COMPLEMENT IF TIME is Completed
RETURN ; Go back

MAIN ; MAIN FUNCTION same as previous

INITIALIZE TIMER
ENABLE TIMER INTERRUPT
WAIT FOR INTERRUPT TF=1

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 Experiment 1 (Contd.)
#define COUNT 5000
unsigned msec_count=0; // msec_count is global variable.
unsigned usect0_count=4;
void timer0ISR(void) org 0x000B
{
usect0_count--;
if(usect0_count==0)
{
msec_count--; // Decrement msec_count on every interrupt.
usect0_count=4
}
TL0=0xBE; // Reload Timer 0 for next msec.
TH0=0xFC;
if(msec_count==0)
{
msec_count=COUNT; // Reload the count.
P3_6_bit=~P3_6_bit; // complement the bit.
}
return; // Back to main.
}
// Timer flags are automatically cleared as soon as timer interrupts are recognized by the
microcontroller.
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 Experiment 1 (Contd.)
void main(void)
{
CLKREG=0; // Select Normal Clock Mode.
TR0_bit=0; // Ensure TIMER 0 is stopped initially.
TMOD=0x01; // Configure TIMER0 in Mode 1.
TL0=0xBE; // Load count for 1 msec.
TH0=0xFC;
msec_count=COUNT; // Load count to get 5 Sec.
EA_bit =1; // Enable EA bit in IE.
ET0_bit=1; // Enable TIMER0 interrupt.
TR0_bit=1; // Start TIMER0.
while(1); // Wait for interrupt.
}
 Experiment 2

Configure Timer 1 of 8051 in Mode 2 to generate

variable delays using interrupt with a resolution of 1
msec and complement the status of LED connected at
Pin P3.5 after every 2.5 seconds.

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 Experiment 3

Configure Timer 0 and Timer 1 of 8051 in Mode 2 to

generate variable delays using interrupt with a
resolution of 1 msec and complement the status of
LED connected at Pin P3.6 after every 5 seconds and
Pin P3.5 after every 2.5 seconds.

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 External Interrupts

EA

P3.2
INT 0 IE0 EX0 0003H

TIMER 0 TF0 ET0 000BH

P3.3
INT 1 IE1 EX1 0013H

TIMER 1 TF1 ET1 001BH

UART 0023H
RI/TI ES
TX / RX

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 TCON: Interrupt Triggering & Flag SFR
Byte Address: 88H

Bit Address 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H

Bit No 7 6 5 4 3 2 1 0
Designation TF1 TR1 TF0 TRO IE1 IT1 IE0 IT0

• TF / TR – Timer Over Flow / Timer RUN.

• IEx – External Interrupt EDGE Detect Flag.
− 1: Interrupting edge detected (i.e. interrupt request present)
− 0: No interrupt request detected.
• ITx – External Interrupt TRIGGER Type.
− 1: -ve Edge Triggered interrupt.
− 0: LOW Level Triggered Interrupt (Default).

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 Experiment 4

Configure 8051 in such a way that whenever external

INT0 occurs, LED at Pin P2.4 toggles its status.

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 Experiment 4 (Contd.)
void external0ISR(void) org 0x0003
{
unsigned char i=0;
P2_4_bit=~P2_4_bit; // complement the bit.
for(i=0;i<64;i++); // Wait for some time.
return; // Back to main.
}

void main(void)
{
EA_bit =1; // Enable EA bit in IE.
IT0_bit=1; // Configure INT0 as Edge triggered interrupt.
EX0_bit =1; // Enable INT0 interrupt through IE.
while(1); // Wait for interrupt.
}
 Experiment 5

Configure 8051 to respond to external edge triggered

interrupts INT0 & INT1. The system should maintain an
integer count that is incremented by 1 on the arrival of
INT0 and the count is decremented by 1 on the arrival of
INT1. Display the count value at Port 2 LEDs.

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 Experiment 5 (Contd.)
unsigned count=0; // Count is global variable.
void external0ISR(void) org 0x0003 // Increment the count
{
unsigned char i=0;
count++; // Increment the count by 1.
P2=~count; // Display Count at Port 2.
for(i=0;i<64;i++); // Wait for some time.
return; // Back to main.
}

void external1ISR(void) org 0x0013 // Decrement the count

{
unsigned char i=0;
count--; // Decrement the count by 1.
P2=~count; // Display Count at Port 2.
for(i=0;i<64;i++); // Wait for some time.
return; // Back to main.
}
 Experiment 5 (Contd.)
void main(void)
{
EA_bit =1; // Enable EA bit in IE.
IT0_bit=1; // Configure INT0 as Edge triggered
interrupt.
IT1_bit=1; // Configure INT1 as Edge triggered
interrupt.
EX0_bit =1; // Enable INT0 interrupt through IE.
EX1_bit =1; // Enable INT0 interrupt through IE.
while(1); // Wait for interrupt.
}
 Experiment 6

Configure 8051 to respond to external edge triggered

interrupts INT0 & INT1. The system should maintain an
integer count that is incremented by 1 on the arrival of
INT0 and the count is decremented by 1 on the arrival of
INT1. Display the count value on 7 Segment display digits.

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