EEE311

Digital Electronics
Lecture 12 – 31/10/2022

Dr. MD. AMIRUL ISLAM

Associate Professor
EEE, BSMRSTU, Gopalganj
FLIP-FLOPS (FF)
AND
RELATED DEVICES

2
 NAND GATE LATCH (SR Latch)

S
Qn+1 S R Qn+1 n+1 State

0 0 1 1 INVALID

0 1 1 0 SET
n+1
1 0 0 1 RESET

R 1 1 Qn n No change / HOLD
NAND Gate Latch

3
 Clocked S-R Flip-Flop

CLK S R Qn+1 n+1 State

0 X X Qn n No change
1 0 0 1 1 No change
1 0 1 0 1 RESET
1 1 0 1 0 SET
S-R latch
1 1 1 1 1 INVALID

https://www.youtube.com/watch?v=dbmSWwu-RGA
4
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

X 1 0 X X Qn n No change

0
X 1 S-R latch

S-R Latch Truth Table

5
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

0 1
1 0 0 Qn n No change
1

0 1 S-R latch

S-R Latch Truth Table

6
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

0
0 1 10

1
1 0 1 0 1 RESET
1 0? S-R latch 01
1
Assume
S-R Latch Truth Table

7
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

1
0 1 0

1
1 0 1 0 1 RESET
1 1? S-R latch 1
0
Assume
S-R Latch Truth Table

8
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

0
1 1? 1

0 1 S-R latch 0 1 1 0 1 0 SET

1
Assume
S-R Latch Truth Table

9
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

1
1 0? 01

0 1 S-R latch 10 1 1 0 1 0 SET

0
Assume
S-R Latch Truth Table

10
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

1
1 0? 01

1 ?1 S-R latch 10
0
Assume 1 1 1 n Qn TOGGLE
S-R Latch Truth Table

11
 J-K FLIP-FLOP

CLK J K Qn+1 n+1 State

0
1 1? 10

1 ?0 S-R latch 01
1
Assume 1 1 1 n Qn TOGGLE
S-R Latch Truth Table

12
 J-K FLIP-FLOP – Summary

CLK J K Qn+1 n+1 State

0 X X Qn n No Change
1 0 0 Qn n No change
1 0 1 0 1 RESET
S-R latch 1 1 0 1 0 SET
1 1 1 n Qn TOGGLE

13
 D FLIP-FLOP

The output Q is same as the D-input input when a PGT occurs. Here, D
stands for data.

14
D FLIP-FLOP - Example

15
 D FLIP-FLOP – How?

An edge-triggered (clocked) D flip-flop can be easily obtained by adding a

single NOT gate to the clocked J-K flip-flop.
16
 D FLIP-FLOP – Why?
Q output of this flip-flop is not exactly
same as D input. The output Q only
changes when PGT occurs. This is very
useful for parallel data transfer and
data storage. In the figure, a common
CLK is connected to three D flip-flops.
When the CLK is triggered, the X, Y
and Z input transfers to the Q1,Q2 and
Q3 of the flip-flops at the same time
and can be stored at that time. 17
Thank You