Chapter 4

Reduced Instruction Set Computers

(RISC)

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Outline
 Introduction
 Instruction Execution Characteristics
 Charactestics of RISC
 CISC vrs RISC
 RISC Pipelining

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Introduction
 Reduced Instruction Set Computer (RISC)
represents
◦ An important innovation in computer architecture
◦ It is an alternative processor design philosophy
◦ It is an attempt to produce more CPU power by
simplifying the instruction set of the CPU
 The opposed trend to RISC is that of Complex
Instruction Set Computer (CISC)

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Introduction…
 In order to improve efficiency of software
development:
◦ powerful high-level programming languages have
been developed (e.g., C++, Java)
 Allow programmer express algorithm more concisely
 Support naturally the use of:
 Structured programming or object-oriented design
 Support higher levels of abstraction
 This evolution has increased the “semantic
gap” between programming languages and
machine languages

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Introduction…
 Semantic gap
◦ The difference between the operations provided in HLLs
and those provided in computer architecture

 To close this gap

◦ Designers/Architects responded with machines that
provide better support for HLLs
 CISC

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Introduction…
 Main features of CISC
◦ A large number of instructions (>200)
◦ Complex instructions and data types
◦ Many and complex addressing modes
 To efficiently support the manipulation of complex
data structures such as multidimensional arrays and
structures
◦ Direct hardware implementations of high-level
language statements:
 For example
 CASE (switch) on VAX
 Loop instruction on Pentium

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Introduction…
 Main features of CISC….
◦ Microprogramming techniques are used so that
complicated instructions can be implemented
 In a cost effective way
 Using microcode

◦ Memory bottleneck is a major problem, due to

 complex addressing modes and
 multiple memory accesses per instruction

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Introduction…
 Arguments for CISC
◦ Ease compiler Writing
 A rich instruction set should simplify the compiler by having instructions
which match the high-level language statements
 This works fine if the number of HLLs is very small

◦ Improve Execution Efficiency

 by implementing complex operations in microcode rather than
machine code

◦ Programs have better performance

 Since the programs are smaller in size, they have better performance:
 They take up less memory space and need fewer instruction fetch
cycles
 Fewer number of instructions are executed, which may lead to smaller
execution time

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Introduction…
 Problems With CISC
◦ A large instruction set requires complex and
potentially time consuming hardware steps to decode
and execute the instructions

◦ Complex machine instructions may not match HLL

statements exactly, in which case they may be of little
use
 This will be a major problem if the number of languages
is getting bigger
 Compilers mostly ignore these instructions
 Due to different semantics used by various HLLs
 Tend to synthesize the code using simpler instructions

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Introduction…
 Problems With CISC…
◦ Instruction sets designed with specialized
instructions for several high-level languages will
not be efficient when executing program of a given
language

◦ Complex design tasks

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Evaluation of Program Execution
 A number of studies conducted over years
◦ To understand execution behavior of machine instruction
sequences generated from HLL programs
◦ To analyze the behavior of HLL programs

 Result of the studies

◦ Inspired researches to look for different approach
 To make the architecture that supports the HLL simpler than
more complex

 The Studies in the next few slides

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Evaluation of Program Execution
 What are programs doing most of the time?

 Aspects of computation of interest:

◦ Operations performed: (Frequency)
 Determine the function to be performed by the CPU and its
interaction with memory
◦ Operands used: (Type and Frequency)
 Determine the memory organization for storing them
 Determine the addressing mode for accessing them
◦ Execution sequencing: (Control flow frequency)
 Determine the control and pipeline organization
 branches
 loops
 subprogram calls

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Evaluation Results
 Operations
◦ Table shows which types of HLL statements occurs most
often and therefore must be supported in optimal fashion

◦ Results
 Assignment statement predominates
 Suggests a simple movement of data is of high importance
 Large number of conditional statements (IF, Loop)
 Suggests sequence control mechanism of the instruction set is
important

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Evaluation Results…
 Operations …
◦ Table shows which types of HLL statements causes the
execution of the most machine language instructions

◦ Results
 Procedure call statements are the most time consuming
operations of HLL programs
 constitute about 12-15% of HLL statement but
 constitute 31-32% of total machine instructions
 Generates nearly half - 45% of all memory references

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Evaluation Results…
 Operations …
◦ Addressing modes:
 the majority of instructions uses simple
addressing modes
 complex addressing modes
 (memory indirect, indexed + indirect, etc.) are
only used by ~18% of the instructions

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Evaluation Results…
 Operations …
◦ Conclusion
 Target architectural implementation to support these
operations well

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Evaluation Results…
 Operand types:
◦ 74-80% of the operands are scalars
 integers, reals, characters, etc…
 about 80% of the scalars are local variables
◦ the rest (20-26%) are arrays/structures
 90% of them are global variables

 Conclusion:
◦ The majority of operands are local variables of
scalar type, which can be stored in registers

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Evaluation Results…
 Execution Sequencing --- Procedure calls
◦ Seen that procedure calls are the most time
consuming operations in HLLS
◦ Statistics on procedure calls
 98% of dynamically called procedures passed
fewer than 6 parameters
 92% use less than 6 local scalar variables
 Implies about activation record size
 Rare to have a long sequence of procedure calls
followed by returns
 Depth of nesting was typically rather low

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Evaluation Conclusion
An overwhelming dominance of Simple
(ALU and move) operations over complex
operations
Dominance of simple addressing
modes
Large frequency of operand accesses;
on average each instruction references
1.9 operands

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Evaluation Conclusions …
 Most of the referenced operands are scalars
(can be stored in registers) and are local
variables or parameters

 Optimizing the procedure CALL/RETURN

mechanism promises large benefits in speed

 The RISC computers are developed to take

advantages of the above results, and thus
delivering better performance!

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RISC Characterstics
 A small number of simple instructions (<100)
◦ Simple and small decode and execution hardware are
required
◦ A hard-wired controller is needed, rather than using
microprogramming
◦ The CPU takes less silicon area to implement, and runs also
faster
 Execution of one instruction per clock cycle

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RISC Characterstics
 The instruction pipeline performs more efficiently
due to simple instructions and similar execution
patterns

 Complex operations are executed as a sequence of

simple instructions
◦ In the case of CISC they are executed as one single or a few
complex instructions

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RISC Characteristics …
 Load-and-store architecture
◦ Only LOAD and STORE instructions reference data in memory
◦ All other instructions operate only with registers
 Register- to-register instructions
 Only a few simple addressing modes are used
◦ E.g. register, direct, register indirect, displacement
 Instructions are of fixed length and uniform format
◦ Loading and decoding of instructions are simple and fast
◦ It is not needed to wait until the length of an instruction is
known in order to start decoding it.
◦ Decoding is simplified because the opcode and address
fields are located in the same position for all instructions

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RISC Characteristics …
 A large number of registers is available
◦ Variables and intermediate results can be stored in
registers and do not require repeated loads and stores
from/to memory
◦ All local variables of procedures and the passed parameters
can be stored in registers
 The large number of registers is due to that the
reduced complexity of the processor leaves silicon
space on the chip to implement them
◦ This is usually not the case with CISC machines

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RISC Characteristics …
 Register Windows
◦ A large number of registers is usually very useful
◦ However, if contents of all registers must be saved at every
procedure call, more registers mean longer delay
◦ A solution to this problem is to divide the register file into a
set of fixed-size windows
 Each window is assigned to a procedure
 Windows for adjacent procedures are overlapped to allow
parameter passing

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RISC Characteristics …
 Register Windows
◦ A large number of registers is usually very useful
◦ However, if contents of all registers must be saved at every
procedure call, more registers mean longer delay.
◦ A solution to this problem is to divide the register file into a
set of fixed-size windows.
 Each window is assigned to a procedure.
 Windows for adjacent procedures are overlapped to allow
parameter passing

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Main Advantages of RISC
 Best support is given by optimizing most
used and most time consuming architecture
aspects
◦ Frequently executed instructions
◦ Memory reference
◦ Procedure call/return
◦ Pipeline design
 Less design complexity, reducing design cost,
and reducing the time between designing and
Marketing

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Criticisms of RISC
 An operation might need two, three, or more
instructions to accomplish
◦ More memory access might be needed
◦ Execution speed may be reduced in certain
applications
 It usually leads to longer programs, which needs
larger memory space to store
 Difficult to program machine codes and assembly
programs
◦ More time consuming

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RISC vrs CISC
 Studies have shown that benchmark
programs run often faster on RISC processors
than on CISC machines
 However, it is difficult to identify which RISC

feature really produces the higher

performance
 Some "CISC fans" argue that the higher speed

is not produced by the typical RISC features

but because of technology, better compilers,
etc…

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RISC vrs CISC…
 An argument in favor of the CISC:
◦ The simpler RISC instruction set results in a larger
memory requirement compared with the CISC case

 Most recent processors are not typical RISC or

CISC, but combine advantages of both
approaches
◦ E.g. PowerPC and Pentium II

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CISC and RISC Examples

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Reading Assignment
 Pipelining in RISC processors
◦ (Read Chapter 13 --- of William Stallings)

 Compare and contrast the use of large register file versus

cache in RISC processor

 Compare and Contrast RISC designs based on

◦ Large register file
◦ Compiler optimization of small register files

 Study characteristics of processors belonging to each group:

◦ RISC processors
 MIPS, SPARC, Itanium, PowerPC
◦ CISC processors
 Intel x386, Pentium

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Summary
 Both RISCs and CISCs try to reduce the semantic gap, with
different approaches.
◦ CISCs follow the traditional way of implementing more and more
complex instructions.
◦ RISCs try to simplify the instruction set, while improving the instruction
execution performance.
 Innovations in RISC architectures are based on a close analysis
of typical programs
 The main features of RISC architectures are:
◦ reduced number of simple instructions, few addressing modes;
◦ instructions with fixed length and format, load store architecture;
◦ a large number of registers.
 RISCs support efficient implementation of pipelining
 Most modern architectures often include both RISC and
CISC features.

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