SRI VENKATESWARA COLLEGE OF ENGINEERING AND

TECHNOLOGY

Synthesis of Approximate
Parallel-Prefix Adders
 AIM OF THE PROJECT

 Performing image addition involves designing a parallel-prefix adder.

 To design parallel-prefix adder, which is a digital circuit that adds multiple binary numbers in parallel.
 It computes carry signals simultaneously using a prefix computation tree, reducing delay and speeding up addition
compared to ripple-carry adders.
 To design the approximate adder that sacrifices precision for better performance, power efficiency, or area utilization. It's
designed for applications where exact accuracy isn't crucial, like machine learning or multimedia processing, to optimize
energy consumption and speed.
 ABSTRACT

 Recent advancements prioritize speed and efficiency over absolute accuracy in computing, highlighting
approximate computation's potential for enhancing energy efficiency. This paradigm shift involves
designing hardware units to deliver sufficiently accurate results for tasks, enabling exploration of novel
approaches aimed at maximizing efficiency. This work delves into the synthesis of approximate parallel-
prefix adders, a crucial component in many computational systems. Instead of adhering to specific
architectures, the approach introduces a synthesizer capable of generating a range of solutions that meet
the designer's requirements Unlike traditional methods that focus on specific architectures, the
introduced synthesizer enables automatic exploration of the design space. This approach yields adders
with varying characteristics such as delay, area, and error trade-offs, allowing for optimal solutions in
different scenarios. By embracing automatic design space exploration, designers can uncover solutions
that may not have been achievable with conventional parallel-prefix architectures. This flexibility opens
avenues for innovation and efficiency improvements in computational hardware design.
 OBJECTIVE
 Investigate methods to enhance the speed and efficiency of parallel prefix adders while
maintaining accuracy.
 Develop techniques to minimize the hardware footprint of parallel prefix adders to
optimize chip area utilization.
 INTRODUCTION

 Approximate computing explores the trade-off between energy and quality by allowing hardware components to compute
potentially inaccurate results, aiming to conserve energy. Designing approximate hardware units presents numerous design
choices, such as removing transistors from cells or eliminating gates and flip-flops from a design's netlist.
 In the realm of digital signal processing and computer arithmetic, the efficiency of arithmetic operations is paramount for
achieving high performance and energy efficiency.
 Among these operations pivotal in numerous computing systems, from simple microcontrollers to complex graphics
processing units (GPUs) and digital signal processors (DSPs).
 The quest for optimizing adders has led to the exploration of various designs, including the parallel-prefix adders (PPAs),
known for their scalability and efficiency in handling large operands.
 LITERATURE SURVEY
Paper Title & Year Methods used Key Contributions
Marylène, Cloitre. (2023). Approximate • The paper studies and compares •The paper uses HDLs and design
Adder Circuits: A Comparative Analysis different types of parallel prefix compiler for implementation and
and Evaluation. Algorithms for adders. synthesis.
intelligent systems, doi: 10.1007/978- • The feasibility of performing •Error characterization is done using
981-19-8742-7_42 addition without using carry is MATLAB.
also analyzed.

(2023). AxPPA: Approximate Parallel Addition units are essential in error- • Introduction of approximate parallel
Prefix Adders. doi: tolerant applications and other math prefix adders (AxPPAs)
10.1109/tvlsi.2022.3218021 operations. • Comparison of AxPPAs with
Approximate PPAs (AxPPAs) are energy-efficient approximate adders
introduced by exploiting (AxAs)
approximations in prefix operators.
Paper Title & Year LITERATURE
Methods used SURVEYKey Contributions
Anagha, M. (2023). Comparative Study • Comparative study of parallel •The paper studies and compares
of Parallel Prefix Adders Based on prefix adders based on carry different types of parallel prefix adders.
Carry Propagation and Sum propagation and sum propagation. •The feasibility of performing addition
Propagation. doi: • Ladner-Fischer, Kogge-Stone, without using carry is also analyzed.
10.1109/PICC57976.2023.10142543 Brent-Kung, Knowles, and Roy-
auto synthesis adders compared.

Kristine, Lund. (2023). Analysis of the ALU and adder circuit are essential • The paper reviews classical addition
Efficiency of Parallel Prefix Adders. components of processing units. methods and evaluates their
Cognitive science and technology, doi: Various methods have been efficiency.
10.1007/978-981-19-8086-2_11 developed to maximize efficiency of • The paper analyzes the performance
addition. of different parallel prefix adders.
 LITERATURE SURVEY
Paper Title & Year Methods used Key Contributions
Sandeep, S.., K., V.. (2022). • Design implementation, •Design implementation and
Synthesis and fpga validation of functionality testing, design functionality testing of various n-
parallel prefix adders. International synthesis, and bitstream bit adder architectures.
journal of advanced research, doi: generation •Synthesis and bitstream generation
10.21474/ijar01/15539 • Various n-bit adder of adders using Verilog HDL and
architectures including RCA, Xilinx Vivado
CLA, CSkA, and KSA
METHODOLOGY

• Design the Circuits for IMAGE Fusion

application
• Evaluating through suitable adders
• Applying Approximation in the adders
• Comparing Area, Delay between existing and
proposed systems
• Calculating the PSNR between existing and
proposed system images.
 PROBLEM STATEMENT

 Ripple Carry Adders (RCA) suffer from delays increasing with input size, critical path issues due to carry chains,
high power consumption, inefficient use of chip space, and limited parallelism. These challenges prompt
exploration of alternative adder designs to improve performance and efficiency in digital systems.
 Carry Look ahead Adders (CLA) face challenges including increased area overhead, design complexity, potential
power consumption, limited scalability, and a trade-off between speed and area efficiency.
 EXISTING SYSTEM

 Traditional adders are designed to be completely accurate, which means they use more energy and
take up more space on a chip
 Some existing approximate adders shorten the carry chain or remove parts of the adder to save energy,
but this can lead to more errors.
 State-of-the-art approaches often focus on specific architectures, which limits the exploration of
different designs and potentially misses out on finding the best balance between accuracy, area, and
energy.
EXISTING DIAGRAM
 DISADVANTAGES
 The additional logic and parallelism in parallel prefix adders may lead to increased power
consumption compared to simpler adder designs, impacting energy efficiency.
 Parallel prefix adders are not inherently designed for approximation tasks. Incorporating
approximation methods would require significant modifications to the adder design,
potentially increasing complexity and introducing challenges related to accuracy,
reliability, and performance trade-offs.
 By focusing on specific architectures, current methods may not find the most efficient
design for a given application, which could lead to either more errors or higher energy
use than necessary.
 The existing approximate adders might not be flexible enough to meet different design
criteria, such as varying levels of accuracy or energy efficiency for different applications
 PROPOSED SYSTEM

 The proposed system is about making adders that can do math in a way that’s very efficient for certain tasks,
which can save energy and space on a chip.
 Instead of sticking to one design, this system can create many different adders that fit what the designer
wants, like time complex and computation complex.
 They also use a smart way to build the adders that lets them mix accurate and less accurate parts to get the
best balance for different jobs, like filtering pictures or recognizing things in images
PROPOSED SYSTEM ARCHITECTURE

15
 PROPOSED SYSTEM

 The proposed system aims to design adders that can perform calculations that are good enough for certain
tasks, which helps save energy and space on computer chips.
 It allows for the creation of many different adder designs that can be tailored to what the designer needs,
such as speed, size, and accuracy
 It uses a smart design approach that combines accurate and less accurate parts to find the best balance for
different jobs like picture filtering or recognizing images.
 ADVANTAGES

 Speed of operation
 Trade-off between Accuracy and Performance
 Adaptability to Error Resilience
 TOOLS USED

 Verification Tool
 ModelSim 6.4c
 Synthesis Tool
• Xilinx ISE 13.2
 Image operation
• MATLAB (Online)
 Xilinx ISE 7.1i

 Create NEW project

 Select the FPGA device and Verilog Language
 Describe the Systems Inputs and Outputs
 Write the Verilog code in Data flow and Gate level modeling for the 8bit Adders
 Get the Synthesis Report.
 SYNTHESIS REPORT EXISTING

Selected Device : 3s100evq100-4

Number of Slices : 9 out of 960 1%
Number of 4 input LUTs : 16 out of 1920 0%
Number of bonded IOBs : 25 out of 66 36%
========================================================================
=
TIMING REPORT
Clock Information:
---------------
Speed Grade: -4
Maximum combinational path delay: 19.868ns
 SYNTHESIS REPORT PROPOSED

Selected Device : 3s100evq100-4

Number of Slices : 9 out of 960 1%
Number of 4 input LUTs : 16 out of 1920 0%
Number of bonded IOBs : 25 out of 66 36%
========================================================================
=
TIMING REPORT
Clock Information:
---------------
Speed Grade: -4
Maximum combinational path delay: 19.868ns
SYNTHESIS RTL
 ModelSim 6.4c

 Simulate model-sim from the Xilinx

 Apply the Desired input sample
 The Output wave form for the corresponding inputs will be generated
Simulation output
Simulation output
 MATLAB
 Open The MATLAB ONLINE
 UPLOAD THE IMAGE AS THE TEXT FILE GENERATED IN THE MODELSIM
 CONVERT THE TEXT IN TO IMAGE CALCULATE PSNR
MATLAB
 MATLAB

INPUT1 INPUT2 IMAGE FUSION IMAGE FUSION

USING APPROXIMATE ADDERS

Image addition is often employed in remote sensing and medical imaging to fuse multiple images acquired from
different sensors or modalities. This can help in improving the overall quality of the image and extracting useful
information from different sources, which can be useful for watermarking, adding logos, or creating overlays for
user interfaces.
 IMAGE OUTPUTS

INPUT1 INPUT2 EXISTING SYSTEM PROPOSED SYSTEM

 FUTURE WORK
 The approximate circuit are used in various image applications like edge detection, Haar
wavelet transforms, image division, deep learning classification with image, etc.
 CONCLUSION

 Approximation is applied by summing PPs and mapping carry bits.

 Improved energy savings with smaller reduction in accuracy.

 Proposed method: Approximate with Error Correction

 Proposed 8-bit Parallel prefix provide lower latency and higher throughput.
 REFERENCE

[1] P. Stanley-Marbell et al., “Exploiting errors for efficiency: A survey from circuits to applications,” ACM Comput. Surv., vol. 53, no. 3, pp. 1–39, May
2021.

[2] M. Pashaeifar, M. Kamal, A. Afzali-Kusha, and M. Pedram, “A theoretical framework for quality estimation and optimization of DSP applications using
low-power approximate adders,” IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 66, no. 1, pp. 327–340, Jan. 2019.

[3] V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, “Low-power digital signal processing using approximate adders,” IEEE Trans. Comput.-Aided
Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124–137 Jan. 2013.

[4] J. Schlachter, V. Camus, K. V. Palem, and C. Enz, “Design and applications of approximate circuits by gate-level pruning,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 25, no. 5, pp. 1694–1702, May 2017.
 THANK
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