Combinational Logic

Combinational Logic
Logic circuits for digital systems may be
combinational or sequential.
A combinational circuit consists of input variables,
logic gates, and output variables.

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 Design Procedure
The design procedure for combinational logic circuits are:

Determine required number of inputs and outputs from the

specifications.
Derive the truth table for each of the outputs based on their
relationships to the input.
Simplify the Boolean expression for each output. Use
Karnaugh Maps or Boolean algebra.
Draw a logic diagram that represents the simplified Boolean
expression.

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 Half Adder
A combinational circuit that performs the addition of two bits
is called a half adder.
The truth table for the half adder is listed below:

x y S C
0 0 0 0
x \ 0y 1
0 1 1 0
1 0
1 0 1 0
1 1 0 1 S = x’y + xy’

x \ 0y 0
S(x,y) = ∑m (1,2) C(x,y) = ∑m (3)
0 1

C = xy
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Implementation of Half-Adder

S = x’y + xy’ or x⊕y

C=xy 5
 Full-Adder
One that performs the addition of three bits(two
significant bits and a previous carry) is a full adder.
x y z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S(x,y,z) = ∑m (1,2,4,7) C(x,y,z) = ∑m (3,5,6,7)

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 Simplified Expressions

S = x’y’z + x’yz’ + xy’z’ + xyz or (x⊕ y⊕z)

C = xy + xz + yz
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 Full-Adder
S = x’y’z + x’yz’ + xy’z’ + xyz
 = x’(y’z+yz’) + x(y’z’+yz)
= x’(y⊕z) + x(y⊕z)’ [y⊕z=A]
= x’A+xA’
= x⊕A
= (x⊕ y⊕z)

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 Full-Adder
S = x’y’z + x’yz’ + xy’z’ + xyz

C = xy + xz + yz

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 Full-Adder
x
S=(x⊕ y⊕z)
y

C = xy + xz + yz

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 Half-Subtractor
One that performs the subtraction of two bits is half
subtractor.
a b D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

D(a,b) = ∑m (1,2) B(a,b) = ∑m (1)

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 Half-Subtractor
D(a,b) = ∑m (1,2) B(a,b) = ∑m (1)

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Half-Subtractor

A⊕B

B
A’B

A’

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 Full-Subtractor
One that performs the subtraction of three bits is Full
subtractor.
a b c D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

D(a,b,c) = ∑m (1,2,4,7) B(a,b,c) = ∑m (1,2,3,7)

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 Full-Subtractor
bc bc
a a

Difference(D)=a⊕b⊕c Borrow(B)=a’c+bc+a’b

D(a,b,c) = ∑m (1,2,4,7) B(a,b,c) = ∑m (1,2,3,7)

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 Full-Subtractor
a
b
c D=a⊕b⊕c

B=a’c+bc+a’b
 Full-Subtractor
a b c

D=a⊕b⊕c

a’

B=a’c+bc+a’b
c

a’

c
Design a full adder circuit using two half adders. Also
verify your answer.
Full Adder Half Adder
S=(x⊕ y⊕z) S=(x⊕ y)
C = xy + xz + yz C = xy

From above circuit: From actual Full adder circuit:

S = (x⊕ y⊕z) C = xy + xz + yz
C = xy+z (x⊕ y) C = xy + xz(y+y’) + yz(x+x’)
= xy+z(x’y+xy’) C = xy+xyz+xy’z+xyz+x’yz
= xy+x’yz+xy’z C = xy+xyz+xy’z+x’yz
C = xy(1+z)+xy’z+x’yz
C = xy+x’yz+xy’z
 Construct a full subtractor circuit using two half
subtractors. Also verify your answer.

x
D= (x⊕ y⊕z)
y

B= x’y+z (x⊕y)’
z

From above circuit: But from the actual Full subtractor circuit:
B = x’y+z (x⊕y)’ B = x’y+yz+x’z
B = x’y+z(xy+x’y’) B = x’y+yz(x+x’)+x’z(y+y’)
B = x’y+xyz+x’y’z B = x’y+xyz+x’yz+x’yz+x’y’z
B = x’y+xyz+x’yz+x’y’z
B = x’y+x’yz+xyz+x’y’z
B = x’y(1+z)+xyz+x’y’z
B = x’y. +xyz+x’y’z verified.
 Code Conversion Circuit
Design a converter circuit which converts BCD to excess 3.

Don’t care conditions:

m10-m15

W(A,B,C,D) = ∑m (5,6,7,8,9)
X(A,B,C,D) = ∑m (1,2,3,4,9)
Y(A,B,C,D) = ∑m (0,3,4,7,8)
Z(A,B,C,D) = ∑m (0,2,4,6,8)
 Code Conversion Circuit
W(A,B,C,D) = ∑m (5,6,7,8,9) X(A,B,C,D) = ∑m (1,2,3,4,9)

W=A+BC+BD X=B’C+B’D+BC’D’
 Code Conversion Circuit
Y(A,B,C,D) = ∑m (0,3,4,7,8) Z(A,B,C,D) = ∑m (0,2,4,6,8)

Y=CD+C’D’ Z=D’
Code Conversion Circuit

BCD to Excess-3 Code Converter Logic Diagram

 Code Conversion Circuit
Design a converter circuit
which converts Binary to Gray.

W(A,B,C,D) = ∑m (8,9,10,11,12,13,14,15)
X(A,B,C,D) = ∑m (4,5,6,7,8,9,10,11)
Y(A,B,C,D) = ∑m (2,3,4,5,10,11,12,13)
Z(A,B,C,D) = ∑m (1,2,5,6,9,10,13,14)
Code Conversion Circuit
 Parity Generator Circuit
EVEN PARITY

P(A,B,C) = ∑m (1,2,4,7)
 Parity Generator Circuit
P(A,B,C) = ∑m (1,2,4,7)

B
P
C

3 bit even parity generator circuit

 Parity Generator Circuit
ODD PARITY

P(A,B,C) = ∑m (0,3,5,6)
 Parity Generator Circuit
P(A,B,C) = ∑m (0,3,5,6)

P=A’B’C’+A’BC+AB’C+ABC’
P=C’(A’B’+AB)+C(A’B+AB’)
P=C’ (A⊕B)’ + C (A⊕B)
P=C’X’ + CX [X= (A⊕B)]
P=C⊙X
P=C⊙(A⊕B)
P= (A⊕B) ⊙ C

B
P
C

3 bit odd parity generator circuit

 Parity Checker Circuit
Even Parity
Check

Cp(A,B,C,P) =
∑m (1,2,4,7,8,11,13,14)

Cp=1 for error

Parity Checker Circuit
Cp(A,B,C,P) = ∑m (1,2,4,7,8,11,13,14)

Cp= (A⊕B)⊕(C⊕P)
 Parity Checker Circuit

B
Cp
C

3 bit message even parity checker circuit

 Parity Checker Circuit
Odd Parity
Check

B
Cp
C

3 bit message odd parity checker circuit

Cp= (A⊕B) ⊙(C⊕P)

 Code Conversion Circuit
Decimal 8 4 -2 -1 2421
A B C D W X Y Z
Design a converter
circuit which converts 0 0 0 0 0 (m0) 0 0 0 0
84 -2 -1 to 2421 code.
1 0 1 1 1 (m7) 0 0 0 1
Don’t care conditions: 2 0 1 1 0 (m6) 0 0 1 0
m1,m2,m3,m12,m13,m14 3 0 1 0 1 (m5) 0 0 1 1
4 0 1 0 0 (m4) 0 1 0 0
5 1 0 1 1 (m11) 1 0 1 1
W(A,B,C,D) = ∑m (8,9,10,11,15)
X(A,B,C,D) = ∑m (4,8,9,10,15)
Y(A,B,C,D) = ∑m (5,6,8,11,15)
6 1 0 1 0 (m10) 1 1 0 0
Z(A,B,C,D) = ∑m (5,7,9,11,15)
7 1 0 0 1 (m9) 1 1 0 1
8 1 0 0 0 (m8) 1 1 1 0
9 1 1 1 1 (m15) 1 1 1 1
 Code Conversion Circuit
Design a converter
circuit which converts
84 -2 -1 to 2421 code.
 Code Conversion Circuit
Design a converter
circuit which converts
84 -2 -1 to 2421 code.
 Code Conversion Circuit
Design a converter
circuit which converts
84 -2 -1 to 2421 code.
 Code Conversion Circuit
Design a converter
circuit which converts
84 -2 -1 to 2421 code.
Seven Segment Display
 Seven Segment Display

• 7 LEDs (light emitting diodes), each one

controlled by an input.

• A seven-segment decoders can be

used to display the decimal
numbers 0-9 and some alpha
characters.
Display Possibilities

Select Alpha Characters

Simple
Messages
 Seven Segment Display

• Input is a 4-bit BCD code  4 inputs (A, B, C, D)

• Output is a 7-bit code (a,b,c,d,e,f,g) that allows for
the decimal equivalent to be

a
Displayed Example:
– Input: (0000)BCD f g b
– Output: 1111110 (a=b=c=d=e=f=1, g=0)
e c
d
Applications
Truth Table for 7 Segment Decoder
Expression for segment g
g (A,B,C,D) = ∑m (2, 3, 4, 5, 6, 8, 9) and ∑d (10,11,12,13,14,15)
Draw K MAP for all the 7 expressions:
a,b,c,d,e,f,g and draw the logic diagram